Search

John J. Tabone Jr.

Examiner (ID: 18928, Phone: (571)272-3827 , Office: P/2117 )

Most Active Art Unit
2111
Art Unit(s)
2117, 2111, 2138, 2133
Total Applications
1407
Issued Applications
1231
Pending Applications
47
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10609205 [patent_doc_number] => 09329232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-03 [patent_title] => 'Scan response reuse method and apparatus' [patent_app_type] => utility [patent_app_number] => 14/735806 [patent_app_country] => US [patent_app_date] => 2015-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 40 [patent_no_of_words] => 9426 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14735806 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/735806
Scan response reuse method and apparatus Jun 9, 2015 Issued
Array ( [id] => 10383856 [patent_doc_number] => 20150268863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'RESOURCE SHARING IN A TELECOMMUNICATIONS ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 14/730874 [patent_app_country] => US [patent_app_date] => 2015-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5458 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14730874 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/730874
Resource sharing in a telecommunications environment Jun 3, 2015 Issued
Array ( [id] => 11846454 [patent_doc_number] => 09734008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-15 [patent_title] => 'Error vector readout from a memory device' [patent_app_type] => utility [patent_app_number] => 14/724901 [patent_app_country] => US [patent_app_date] => 2015-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5648 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14724901 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/724901
Error vector readout from a memory device May 28, 2015 Issued
Array ( [id] => 10368381 [patent_doc_number] => 20150253386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY' [patent_app_type] => utility [patent_app_number] => 14/717632 [patent_app_country] => US [patent_app_date] => 2015-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4791 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14717632 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/717632
Blocking the effects of scan chain testing upon a change in scan chain topology May 19, 2015 Issued
Array ( [id] => 11274421 [patent_doc_number] => 20160336968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'SYSTEM AND METHOD FOR ENCODING AND DECODING USING A PLURALITY OF CONSTELLATIONS WITHIN A SINGLE FEC BLOCK' [patent_app_type] => utility [patent_app_number] => 14/709283 [patent_app_country] => US [patent_app_date] => 2015-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3617 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14709283 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/709283
SYSTEM AND METHOD FOR ENCODING AND DECODING USING A PLURALITY OF CONSTELLATIONS WITHIN A SINGLE FEC BLOCK May 10, 2015 Abandoned
Array ( [id] => 10810210 [patent_doc_number] => 20160156369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-02 [patent_title] => 'DATA PROCESSING DEVICE AND DATA PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 14/905145 [patent_app_country] => US [patent_app_date] => 2015-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 221 [patent_figures_cnt] => 221 [patent_no_of_words] => 56957 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14905145 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/905145
DATA PROCESSING DEVICE AND DATA PROCESSING METHOD May 7, 2015 Abandoned
Array ( [id] => 11903467 [patent_doc_number] => 09772901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'Memory reliability using error-correcting code' [patent_app_type] => utility [patent_app_number] => 14/707471 [patent_app_country] => US [patent_app_date] => 2015-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5993 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14707471 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/707471
Memory reliability using error-correcting code May 7, 2015 Issued
Array ( [id] => 11919128 [patent_doc_number] => 09787327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-10 [patent_title] => 'Low-power partial-parallel chien search architecture with polynomial degree reduction' [patent_app_type] => utility [patent_app_number] => 14/706767 [patent_app_country] => US [patent_app_date] => 2015-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 13786 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14706767 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/706767
Low-power partial-parallel chien search architecture with polynomial degree reduction May 6, 2015 Issued
Array ( [id] => 11846318 [patent_doc_number] => 09733870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-15 [patent_title] => 'Error vector readout from a memory device' [patent_app_type] => utility [patent_app_number] => 14/705115 [patent_app_country] => US [patent_app_date] => 2015-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5618 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14705115 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/705115
Error vector readout from a memory device May 5, 2015 Issued
Array ( [id] => 11903465 [patent_doc_number] => 09772899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'Error correction code management of write-once memory codes' [patent_app_type] => utility [patent_app_number] => 14/703714 [patent_app_country] => US [patent_app_date] => 2015-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6390 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14703714 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/703714
Error correction code management of write-once memory codes May 3, 2015 Issued
Array ( [id] => 11126015 [patent_doc_number] => 20160322990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-03 [patent_title] => 'TRACKING AND USE OF TRACKED BIT VALUES FOR ENCODING AND DECODING DATA IN UNRELIABLE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/701130 [patent_app_country] => US [patent_app_date] => 2015-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 16946 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14701130 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/701130
Tracking and use of tracked bit values for encoding and decoding data in unreliable memory Apr 29, 2015 Issued
Array ( [id] => 11049718 [patent_doc_number] => 20160246677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'VIRTUAL CHUNK SERVICE BASED DATA RECOVERY IN A DISTRIBUTED DATA STORAGE SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/696001 [patent_app_country] => US [patent_app_date] => 2015-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6776 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14696001 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/696001
Virtual chunk service based data recovery in a distributed data storage system Apr 23, 2015 Issued
Array ( [id] => 10796123 [patent_doc_number] => 20160142280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'PACKET TRACKING IN A VERIFICATION ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 14/672016 [patent_app_country] => US [patent_app_date] => 2015-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 22218 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14672016 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/672016
Packet tracking in a verification environment Mar 26, 2015 Issued
Array ( [id] => 12041120 [patent_doc_number] => 09819362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-14 [patent_title] => 'Apparatus and method for detecting and mitigating bit-line opens in flash memory' [patent_app_type] => utility [patent_app_number] => 14/671140 [patent_app_country] => US [patent_app_date] => 2015-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8313 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14671140 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/671140
Apparatus and method for detecting and mitigating bit-line opens in flash memory Mar 26, 2015 Issued
Array ( [id] => 10793046 [patent_doc_number] => 20160139202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'TESTBENCH BUILDER, SYSTEM, DEVICE AND METHOD INCLUDING LATENCY DETECTION' [patent_app_type] => utility [patent_app_number] => 14/672025 [patent_app_country] => US [patent_app_date] => 2015-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 18810 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14672025 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/672025
Testbench builder, system, device and method including latency detection Mar 26, 2015 Issued
Array ( [id] => 10294283 [patent_doc_number] => 20150179282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'AUTOMATIC TEST-PATTERN GENERATION FOR MEMORY-SHADOW-LOGIC TESTING' [patent_app_type] => utility [patent_app_number] => 14/640601 [patent_app_country] => US [patent_app_date] => 2015-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5462 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14640601 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/640601
Automatic test-pattern generation for memory-shadow-logic testing Mar 5, 2015 Issued
Array ( [id] => 11062038 [patent_doc_number] => 20160259000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-08 [patent_title] => 'COMMUNICATION AND CONTROL TOPOLOGY FOR EFFICIENT TESTING OF SETS OF DEVICES' [patent_app_type] => utility [patent_app_number] => 14/637533 [patent_app_country] => US [patent_app_date] => 2015-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8901 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14637533 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/637533
Communication and control topology for efficient testing of sets of devices Mar 3, 2015 Issued
Array ( [id] => 10292325 [patent_doc_number] => 20150177324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'SCAN TOPOLOGY DISCOVERY IN TARGET SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/637078 [patent_app_country] => US [patent_app_date] => 2015-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8295 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14637078 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/637078
Class T0-T2 and T4 TAPS with, without topology selection logic Mar 2, 2015 Issued
Array ( [id] => 10084560 [patent_doc_number] => 09121906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-01 [patent_title] => 'Semiconductor test system and method' [patent_app_type] => utility [patent_app_number] => 14/637098 [patent_app_country] => US [patent_app_date] => 2015-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 34 [patent_no_of_words] => 11605 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14637098 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/637098
Semiconductor test system and method Mar 2, 2015 Issued
Array ( [id] => 10269071 [patent_doc_number] => 20150154068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-04 [patent_title] => 'MEMORY DEVICE HAVING ADDRESS AND COMMAND SELECTABLE CAPABILITIES' [patent_app_type] => utility [patent_app_number] => 14/617784 [patent_app_country] => US [patent_app_date] => 2015-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5964 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14617784 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/617784
Memory device having address and command selectable capabilities Feb 8, 2015 Issued
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