Search

John J. Tabone Jr.

Examiner (ID: 18928, Phone: (571)272-3827 , Office: P/2117 )

Most Active Art Unit
2111
Art Unit(s)
2117, 2111, 2138, 2133
Total Applications
1407
Issued Applications
1231
Pending Applications
47
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11752305 [patent_doc_number] => 09710318 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Endian configuration memory and ECC protecting processor endianess mode circuit' [patent_app_type] => utility [patent_app_number] => 14/602933 [patent_app_country] => US [patent_app_date] => 2015-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 11725 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14602933 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/602933
Endian configuration memory and ECC protecting processor endianess mode circuit Jan 21, 2015 Issued
Array ( [id] => 11752305 [patent_doc_number] => 09710318 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Endian configuration memory and ECC protecting processor endianess mode circuit' [patent_app_type] => utility [patent_app_number] => 14/602933 [patent_app_country] => US [patent_app_date] => 2015-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 11725 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14602933 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/602933
Endian configuration memory and ECC protecting processor endianess mode circuit Jan 21, 2015 Issued
Array ( [id] => 10378759 [patent_doc_number] => 20150263765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'DATA BLOCK INTERLEAVING AND DEINTERLEAVING METHOD AND APPARATUS FOR COMMUNICATION EQUIPMENTS' [patent_app_type] => utility [patent_app_number] => 14/596709 [patent_app_country] => US [patent_app_date] => 2015-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11553 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14596709 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/596709
Data block interleaving and deinterleaving method and apparatus for communication equipments Jan 13, 2015 Issued
Array ( [id] => 11680301 [patent_doc_number] => 09678832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Storage module and method for on-chip copy gather' [patent_app_type] => utility [patent_app_number] => 14/595939 [patent_app_country] => US [patent_app_date] => 2015-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5693 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14595939 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/595939
Storage module and method for on-chip copy gather Jan 12, 2015 Issued
Array ( [id] => 11346986 [patent_doc_number] => 09531405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Method and system for estimating parameter of data channel model in communication system' [patent_app_type] => utility [patent_app_number] => 14/593417 [patent_app_country] => US [patent_app_date] => 2015-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6683 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14593417 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/593417
Method and system for estimating parameter of data channel model in communication system Jan 8, 2015 Issued
Array ( [id] => 10301210 [patent_doc_number] => 20150186211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'METHOD, DEVICE AND OPERATING SYSTEM FOR PROCESSING AND USING BURN DATA OF NAND FLASH' [patent_app_type] => utility [patent_app_number] => 14/584653 [patent_app_country] => US [patent_app_date] => 2014-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6480 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14584653 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/584653
Method, device and operating system for processing and using burn data of NAND flash Dec 28, 2014 Issued
Array ( [id] => 10982703 [patent_doc_number] => 20160179647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'TEST LOGIC FOR A SERIAL INTERCONNECT' [patent_app_type] => utility [patent_app_number] => 14/581000 [patent_app_country] => US [patent_app_date] => 2014-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10813 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14581000 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/581000
Test logic for a serial interconnect Dec 22, 2014 Issued
Array ( [id] => 10236170 [patent_doc_number] => 20150121165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'EFFICIENT ERROR HANDLING MECHANISMS IN DATA STORAGE SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/581846 [patent_app_country] => US [patent_app_date] => 2014-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5047 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14581846 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/581846
Efficient error handling mechanisms in data storage systems Dec 22, 2014 Issued
Array ( [id] => 11614763 [patent_doc_number] => 09652620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-16 [patent_title] => 'Quantum communication device, quantum communication method, and computer program product' [patent_app_type] => utility [patent_app_number] => 14/579045 [patent_app_country] => US [patent_app_date] => 2014-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 11972 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14579045 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/579045
Quantum communication device, quantum communication method, and computer program product Dec 21, 2014 Issued
Array ( [id] => 10723805 [patent_doc_number] => 20160069954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'SEMICONDUCTOR APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/572929 [patent_app_country] => US [patent_app_date] => 2014-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3975 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14572929 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/572929
SEMICONDUCTOR APPARATUS Dec 16, 2014 Abandoned
Array ( [id] => 10020719 [patent_doc_number] => 09063197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-23 [patent_title] => 'Blocking the effects of scan chain testing upon a change in scan chain topology' [patent_app_type] => utility [patent_app_number] => 14/567266 [patent_app_country] => US [patent_app_date] => 2014-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4789 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14567266 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/567266
Blocking the effects of scan chain testing upon a change in scan chain topology Dec 10, 2014 Issued
Array ( [id] => 10210569 [patent_doc_number] => 20150095560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'PROGRAM-DISTURB MANAGEMENT FOR PHASE CHANGE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/563748 [patent_app_country] => US [patent_app_date] => 2014-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7738 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14563748 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/563748
Program-disturb management for phase change memory Dec 7, 2014 Issued
Array ( [id] => 10531865 [patent_doc_number] => 09258014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-09 [patent_title] => 'Using parity data for concurrent data authentication, correction, compression, and encryption' [patent_app_type] => utility [patent_app_number] => 14/543641 [patent_app_country] => US [patent_app_date] => 2014-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 30560 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14543641 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/543641
Using parity data for concurrent data authentication, correction, compression, and encryption Nov 16, 2014 Issued
Array ( [id] => 11725954 [patent_doc_number] => 09698825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-04 [patent_title] => 'Fast update of data packet checksums' [patent_app_type] => utility [patent_app_number] => 14/521035 [patent_app_country] => US [patent_app_date] => 2014-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4506 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14521035 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/521035
Fast update of data packet checksums Oct 21, 2014 Issued
Array ( [id] => 10329974 [patent_doc_number] => 20150214978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'EFFICIENT INFORMATION RECONCILIATION METHOD USING TURBO CODES OVER THE QUANTUM CHANNEL' [patent_app_type] => utility [patent_app_number] => 14/515296 [patent_app_country] => US [patent_app_date] => 2014-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4234 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14515296 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/515296
Efficient information reconciliation method using turbo codes over the quantum channel Oct 14, 2014 Issued
Array ( [id] => 11946559 [patent_doc_number] => 20170250710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'METHOD AND DEVICE FOR CALCULATING A CRC CODE IN PARALLEL' [patent_app_type] => utility [patent_app_number] => 15/516401 [patent_app_country] => US [patent_app_date] => 2014-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10218 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15516401 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/516401
METHOD AND DEVICE FOR CALCULATING A CRC CODE IN PARALLEL Oct 2, 2014 Abandoned
Array ( [id] => 9807983 [patent_doc_number] => 20150019928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-15 [patent_title] => 'SEMICONDUCTOR TEST SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/504649 [patent_app_country] => US [patent_app_date] => 2014-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11567 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14504649 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/504649
IC test circuitry with tri-state buffer, comparator, and scan cell Oct 1, 2014 Issued
Array ( [id] => 10747249 [patent_doc_number] => 20160093400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'POWER-AWARE MEMORY SELF-TEST UNIT' [patent_app_type] => utility [patent_app_number] => 14/502458 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5947 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14502458 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/502458
Power-aware memory self-test unit Sep 29, 2014 Issued
Array ( [id] => 11201827 [patent_doc_number] => 09432052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Puncture-aware low density parity check (LDPC) decoding' [patent_app_type] => utility [patent_app_number] => 14/501719 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 11232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14501719 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/501719
Puncture-aware low density parity check (LDPC) decoding Sep 29, 2014 Issued
Array ( [id] => 11285497 [patent_doc_number] => 09501351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-22 [patent_title] => 'Memory control unit and data storage device including the same' [patent_app_type] => utility [patent_app_number] => 14/500515 [patent_app_country] => US [patent_app_date] => 2014-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6759 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14500515 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/500515
Memory control unit and data storage device including the same Sep 28, 2014 Issued
Menu