
John J. Tabone Jr.
Examiner (ID: 18928, Phone: (571)272-3827 , Office: P/2117 )
| Most Active Art Unit | 2111 |
| Art Unit(s) | 2117, 2111, 2138, 2133 |
| Total Applications | 1407 |
| Issued Applications | 1231 |
| Pending Applications | 47 |
| Abandoned Applications | 141 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10335383
[patent_doc_number] => 20150220388
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-08-06
[patent_title] => 'Systems and Methods for Hard Error Reduction in a Solid State Memory Device'
[patent_app_type] => utility
[patent_app_number] => 14/178201
[patent_app_country] => US
[patent_app_date] => 2014-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5606
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14178201
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/178201 | Systems and methods for hard error reduction in a solid state memory device | Feb 10, 2014 | Issued |
Array
(
[id] => 9933915
[patent_doc_number] => 20150082107
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-03-19
[patent_title] => 'STATE MACHINE BASED FUNCTIONAL STRESS TESTS'
[patent_app_type] => utility
[patent_app_number] => 14/172887
[patent_app_country] => US
[patent_app_date] => 2014-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 10115
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14172887
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/172887 | STATE MACHINE BASED FUNCTIONAL STRESS TESTS | Feb 3, 2014 | Abandoned |
Array
(
[id] => 13756297
[patent_doc_number] => 10171107
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-01
[patent_title] => Groups of phase invariant codewords
[patent_app_type] => utility
[patent_app_number] => 15/114398
[patent_app_country] => US
[patent_app_date] => 2014-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2626
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15114398
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/114398 | Groups of phase invariant codewords | Jan 30, 2014 | Issued |
Array
(
[id] => 11293523
[patent_doc_number] => 20160343455
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-24
[patent_title] => 'REMAPPING MEMORY LOCATIONS IN A MEMORY ARRAY'
[patent_app_type] => utility
[patent_app_number] => 15/114950
[patent_app_country] => US
[patent_app_date] => 2014-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6955
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15114950
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/114950 | REMAPPING MEMORY LOCATIONS IN A MEMORY ARRAY | Jan 30, 2014 | Abandoned |
Array
(
[id] => 13058469
[patent_doc_number] => 10050645
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-08-14
[patent_title] => Joint encryption and error correction encoding
[patent_app_type] => utility
[patent_app_number] => 15/114501
[patent_app_country] => US
[patent_app_date] => 2014-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3545
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15114501
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/114501 | Joint encryption and error correction encoding | Jan 29, 2014 | Issued |
Array
(
[id] => 10327147
[patent_doc_number] => 20150212151
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-30
[patent_title] => 'System And Method For Scan-Testing Of Idle Functional Units In Operating Systems'
[patent_app_type] => utility
[patent_app_number] => 14/166383
[patent_app_country] => US
[patent_app_date] => 2014-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3378
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14166383
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/166383 | System and method for scan-testing of idle functional units in operating systems | Jan 27, 2014 | Issued |
Array
(
[id] => 10623460
[patent_doc_number] => 09342402
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-05-17
[patent_title] => 'Memory interface with hybrid error detection circuitry for modular designs'
[patent_app_type] => utility
[patent_app_number] => 14/166337
[patent_app_country] => US
[patent_app_date] => 2014-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5964
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 41
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14166337
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/166337 | Memory interface with hybrid error detection circuitry for modular designs | Jan 27, 2014 | Issued |
Array
(
[id] => 10500656
[patent_doc_number] => 09229053
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-01-05
[patent_title] => 'Methods and apparatus for debugging lowest power states in System-On-Chips'
[patent_app_type] => utility
[patent_app_number] => 14/165871
[patent_app_country] => US
[patent_app_date] => 2014-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3796
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14165871
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/165871 | Methods and apparatus for debugging lowest power states in System-On-Chips | Jan 27, 2014 | Issued |
Array
(
[id] => 10570946
[patent_doc_number] => 09294133
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-03-22
[patent_title] => 'Method and apparatus for error correction'
[patent_app_type] => utility
[patent_app_number] => 14/161354
[patent_app_country] => US
[patent_app_date] => 2014-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4781
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14161354
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/161354 | Method and apparatus for error correction | Jan 21, 2014 | Issued |
Array
(
[id] => 9604912
[patent_doc_number] => 20140201594
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-17
[patent_title] => 'Low-Power Low Density Parity Check Decoding'
[patent_app_type] => utility
[patent_app_number] => 14/156733
[patent_app_country] => US
[patent_app_date] => 2014-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4189
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14156733
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/156733 | Low-power low density parity check decoding | Jan 15, 2014 | Issued |
Array
(
[id] => 10569606
[patent_doc_number] => 09292777
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-03-22
[patent_title] => 'Information processing apparatus, information processing method, and storage medium'
[patent_app_type] => utility
[patent_app_number] => 14/157262
[patent_app_country] => US
[patent_app_date] => 2014-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 8037
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14157262
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/157262 | Information processing apparatus, information processing method, and storage medium | Jan 15, 2014 | Issued |
Array
(
[id] => 9829413
[patent_doc_number] => 08938651
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-01-20
[patent_title] => 'Blocking the effects of scan chain testing upon a change in scan chain topology'
[patent_app_type] => utility
[patent_app_number] => 14/149139
[patent_app_country] => US
[patent_app_date] => 2014-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 4762
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14149139
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/149139 | Blocking the effects of scan chain testing upon a change in scan chain topology | Jan 6, 2014 | Issued |
Array
(
[id] => 10309981
[patent_doc_number] => 20150194983
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-09
[patent_title] => 'READ THRESHOLD CALIBRATION FOR LDPC'
[patent_app_type] => utility
[patent_app_number] => 14/148149
[patent_app_country] => US
[patent_app_date] => 2014-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 9582
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14148149
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/148149 | Read threshold calibration for LDPC | Jan 5, 2014 | Issued |
Array
(
[id] => 9645134
[patent_doc_number] => 20140223246
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-08-07
[patent_title] => 'MEMORY, MEMORY CONTROLLER, MEMORY SYSTEM, METHOD OF MEMORY, MEMORY CONTROLLER AND MEMORY SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 14/147063
[patent_app_country] => US
[patent_app_date] => 2014-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 37
[patent_no_of_words] => 19120
[patent_no_of_claims] => 66
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14147063
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/147063 | Memory, memory controller, memory system, method of memory, memory controller and memory system | Jan 2, 2014 | Issued |
Array
(
[id] => 10221684
[patent_doc_number] => 20150106677
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-16
[patent_title] => 'HANDLING ERRORS IN TERNARY CONTENT ADDRESSABLE MEMORIES'
[patent_app_type] => utility
[patent_app_number] => 14/136041
[patent_app_country] => US
[patent_app_date] => 2013-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5970
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14136041
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/136041 | Handling errors in ternary content addressable memories | Dec 19, 2013 | Issued |
Array
(
[id] => 10285766
[patent_doc_number] => 20150170764
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-18
[patent_title] => 'DETECTING MISSING WRITE TO CACHE/MEMORY OPERATIONS'
[patent_app_type] => utility
[patent_app_number] => 14/105443
[patent_app_country] => US
[patent_app_date] => 2013-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8309
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14105443
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/105443 | Detecting missing write to cache/memory operations | Dec 12, 2013 | Issued |
Array
(
[id] => 9410247
[patent_doc_number] => 20140101499
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-04-10
[patent_title] => 'BIT ERROR RATE BASED WEAR LEVELING FOR SOLID STATE DRIVE MEMORY'
[patent_app_type] => utility
[patent_app_number] => 14/101655
[patent_app_country] => US
[patent_app_date] => 2013-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5477
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14101655
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/101655 | Bit error rate based wear leveling for solid state drive memory | Dec 9, 2013 | Issued |
Array
(
[id] => 9410251
[patent_doc_number] => 20140101503
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-04-10
[patent_title] => 'SCAN TOPOLOGY DISCOVERY IN TARGET SYSTEMS'
[patent_app_type] => utility
[patent_app_number] => 14/101871
[patent_app_country] => US
[patent_app_date] => 2013-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8232
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14101871
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/101871 | Scan topology discovery in target systems | Dec 9, 2013 | Issued |
Array
(
[id] => 10080488
[patent_doc_number] => 09118349
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-08-25
[patent_title] => 'Continuous parallel cyclic BCH decoding architecture'
[patent_app_type] => utility
[patent_app_number] => 14/087192
[patent_app_country] => US
[patent_app_date] => 2013-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 4968
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14087192
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/087192 | Continuous parallel cyclic BCH decoding architecture | Nov 21, 2013 | Issued |
Array
(
[id] => 10105687
[patent_doc_number] => 09141469
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-09-22
[patent_title] => 'Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic'
[patent_app_type] => utility
[patent_app_number] => 14/083059
[patent_app_country] => US
[patent_app_date] => 2013-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4709
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14083059
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/083059 | Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic | Nov 17, 2013 | Issued |