Search

John J. Tabone Jr.

Examiner (ID: 1826, Phone: (571)272-3827 , Office: P/2117 )

Most Active Art Unit
2111
Art Unit(s)
2117, 2138, 2111, 2133
Total Applications
1411
Issued Applications
1231
Pending Applications
51
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19971134 [patent_doc_number] => 12339745 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-06-24 [patent_title] => Solid-state drive with multimode compression and error correction [patent_app_type] => utility [patent_app_number] => 18/641942 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 0 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18641942 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/641942
Solid-state drive with multimode compression and error correction Apr 21, 2024 Issued
Array ( [id] => 20389818 [patent_doc_number] => 12489559 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Forward error correction with flexible matrix for dynamic input data rate [patent_app_type] => utility [patent_app_number] => 18/642287 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 12357 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18642287 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/642287
Forward error correction with flexible matrix for dynamic input data rate Apr 21, 2024 Issued
Array ( [id] => 20203074 [patent_doc_number] => 12405853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Data storage device and searching method for reading voltage thereof [patent_app_type] => utility [patent_app_number] => 18/628831 [patent_app_country] => US [patent_app_date] => 2024-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 0 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18628831 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/628831
Data storage device and searching method for reading voltage thereof Apr 7, 2024 Issued
Array ( [id] => 20280856 [patent_doc_number] => 20250306098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => CIRCUITRY INCLUDING SCAN AND NON-SCAN REGISTERS [patent_app_type] => utility [patent_app_number] => 18/620534 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18620534 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/620534
Circuitry including scan and non-scan registers Mar 27, 2024 Issued
Array ( [id] => 19465600 [patent_doc_number] => 20240319270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => RESET FOR SCAN MODE EXIT FOR DEVICES WITH POWER-ON RESET GENERATION CIRCUITRY [patent_app_type] => utility [patent_app_number] => 18/612251 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4817 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18612251 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/612251
Reset for scan mode exit for devices with power-on reset generation circuitry Mar 20, 2024 Issued
Array ( [id] => 19545078 [patent_doc_number] => 20240362114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => MEMORY MANAGEMENT HOLDING LATCH PLACEMENT AND CONTROL SIGNAL GENERATION [patent_app_type] => utility [patent_app_number] => 18/607152 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13218 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18607152 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/607152
MEMORY MANAGEMENT HOLDING LATCH PLACEMENT AND CONTROL SIGNAL GENERATION Mar 14, 2024 Pending
Array ( [id] => 19267640 [patent_doc_number] => 20240211343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => TECHNIQUES FOR INDICATING A WRITE LINK ERROR [patent_app_type] => utility [patent_app_number] => 18/590671 [patent_app_country] => US [patent_app_date] => 2024-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12390 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18590671 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/590671
Techniques for indicating a write link error Feb 27, 2024 Issued
Array ( [id] => 19383110 [patent_doc_number] => 20240272980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => MEMORY DEVICE AND REPAIR METHOD WITH COLUMN-BASED ERROR CODE TRACKING [patent_app_type] => utility [patent_app_number] => 18/444320 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5954 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444320 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/444320
Memory device and repair method with column-based error code tracking Feb 15, 2024 Issued
Array ( [id] => 20273702 [patent_doc_number] => 12443484 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Apparatuses and methods for variable input ECC circuits [patent_app_type] => utility [patent_app_number] => 18/444482 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1396 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444482 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/444482
Apparatuses and methods for variable input ECC circuits Feb 15, 2024 Issued
Array ( [id] => 20166174 [patent_doc_number] => 20250258221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => CO-DEBUG OF PROCESSING CONDITIONS OF LOGIC DEVICES [patent_app_type] => utility [patent_app_number] => 18/438917 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438917 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/438917
Co-debug of processing conditions of logic devices Feb 11, 2024 Issued
Array ( [id] => 19633192 [patent_doc_number] => 20240411641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => STORAGE DEVICE INCLUDING A READ RECLAIM MODULE AND A RECLAIM OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/420849 [patent_app_country] => US [patent_app_date] => 2024-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10039 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420849 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/420849
Storage device including a read reclaim module and a reclaim operation method thereof Jan 23, 2024 Issued
Array ( [id] => 19573822 [patent_doc_number] => 20240378114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => DECODER FOR INTERLEAVED REED-SOLOMON (IRS) WITH ERASURE/COLLABORATIVE [patent_app_type] => utility [patent_app_number] => 18/415631 [patent_app_country] => US [patent_app_date] => 2024-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9604 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415631 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415631
Decoder for interleaved Reed-Solomon (IRS) with erasure/collaborative Jan 16, 2024 Issued
Array ( [id] => 19302181 [patent_doc_number] => 20240230758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => SAVING AND RESTORING SCAN STATES [patent_app_type] => utility [patent_app_number] => 18/406067 [patent_app_country] => US [patent_app_date] => 2024-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406067 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406067
Saving and restoring scan states Jan 4, 2024 Issued
Array ( [id] => 19941554 [patent_doc_number] => 12313680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Automatic test pattern generation-based circuit verification method and apparatus [patent_app_type] => utility [patent_app_number] => 18/397481 [patent_app_country] => US [patent_app_date] => 2023-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 13281 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18397481 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/397481
Automatic test pattern generation-based circuit verification method and apparatus Dec 26, 2023 Issued
Array ( [id] => 19848065 [patent_doc_number] => 20250093416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => Scan Data Transfer Circuits for Multi-die Chip Testing [patent_app_type] => utility [patent_app_number] => 18/391145 [patent_app_country] => US [patent_app_date] => 2023-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18391145 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/391145
Scan data transfer circuits for multi-die chip testing Dec 19, 2023 Issued
Array ( [id] => 20160070 [patent_doc_number] => 12386698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Memory chips and operating methods thereof [patent_app_type] => utility [patent_app_number] => 18/544572 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2575 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18544572 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/544572
Memory chips and operating methods thereof Dec 18, 2023 Issued
Array ( [id] => 19174548 [patent_doc_number] => 20240160522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => ERRONEOUS BIT DISCOVERY IN MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/540351 [patent_app_country] => US [patent_app_date] => 2023-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18540351 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/540351
Erroneous bit discovery in memory system Dec 13, 2023 Issued
Array ( [id] => 20159353 [patent_doc_number] => 12385974 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Device and method for providing physically unclonable function with high reliability [patent_app_type] => utility [patent_app_number] => 18/538692 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 4438 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18538692 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/538692
Device and method for providing physically unclonable function with high reliability Dec 12, 2023 Issued
Array ( [id] => 20609935 [patent_doc_number] => 12585537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Systems and methods for verifying data in memory [patent_app_type] => utility [patent_app_number] => 18/534458 [patent_app_country] => US [patent_app_date] => 2023-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9737 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18534458 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/534458
Systems and methods for verifying data in memory Dec 7, 2023 Issued
Array ( [id] => 19204803 [patent_doc_number] => 20240176702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => Data Storage Based On Characteristics of Storage Media [patent_app_type] => utility [patent_app_number] => 18/530457 [patent_app_country] => US [patent_app_date] => 2023-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18530457 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/530457
Data storage based on characteristics of storage media Dec 5, 2023 Issued
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