Search

John J. Tabone Jr.

Examiner (ID: 18928, Phone: (571)272-3827 , Office: P/2117 )

Most Active Art Unit
2111
Art Unit(s)
2117, 2111, 2138, 2133
Total Applications
1407
Issued Applications
1231
Pending Applications
47
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9109981 [patent_doc_number] => 20130283113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'Systems and Methods for Back Step Data Decoding' [patent_app_type] => utility [patent_app_number] => 13/452733 [patent_app_country] => US [patent_app_date] => 2012-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10113 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13452733 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/452733
Systems and methods for back step data decoding Apr 19, 2012 Issued
Array ( [id] => 9652259 [patent_doc_number] => 08806294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-12 [patent_title] => 'Error detection within a memory' [patent_app_type] => utility [patent_app_number] => 13/452501 [patent_app_country] => US [patent_app_date] => 2012-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7176 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13452501 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/452501
Error detection within a memory Apr 19, 2012 Issued
Array ( [id] => 9404798 [patent_doc_number] => 08694862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-08 [patent_title] => 'Data processing apparatus using implicit data storage data storage and method of implicit data storage' [patent_app_type] => utility [patent_app_number] => 13/451728 [patent_app_country] => US [patent_app_date] => 2012-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 10620 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13451728 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/451728
Data processing apparatus using implicit data storage data storage and method of implicit data storage Apr 19, 2012 Issued
Array ( [id] => 8466942 [patent_doc_number] => 20120272110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-25 [patent_title] => 'Test Generator For Low Power Built-In Self-Test' [patent_app_type] => utility [patent_app_number] => 13/451527 [patent_app_country] => US [patent_app_date] => 2012-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4995 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13451527 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/451527
Test generator for low power built-in self-test Apr 18, 2012 Issued
Array ( [id] => 10036049 [patent_doc_number] => 09077380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-07 [patent_title] => 'Data processing device and data processing method' [patent_app_type] => utility [patent_app_number] => 14/111045 [patent_app_country] => US [patent_app_date] => 2012-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 159 [patent_figures_cnt] => 178 [patent_no_of_words] => 69029 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14111045 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/111045
Data processing device and data processing method Apr 18, 2012 Issued
Array ( [id] => 9044240 [patent_doc_number] => 20130246878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'STATISTICAL DISTRIBUTION BASED VARIABLE-BIT ERROR CORRECTION CODING' [patent_app_type] => utility [patent_app_number] => 13/450963 [patent_app_country] => US [patent_app_date] => 2012-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5858 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13450963 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/450963
Statistical distribution based variable-bit error correction coding Apr 18, 2012 Issued
Array ( [id] => 8816575 [patent_doc_number] => 20130117620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-09 [patent_title] => 'MEMORY SYSTEM AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/449501 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 19389 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13449501 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/449501
Memory system and operating method thereof Apr 17, 2012 Issued
Array ( [id] => 9109982 [patent_doc_number] => 20130283114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'Systems and Methods for Locating and Correcting Decoder Mis-Corrections' [patent_app_type] => utility [patent_app_number] => 13/450289 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7199 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13450289 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/450289
Systems and methods for locating and correcting decoder mis-corrections Apr 17, 2012 Issued
Array ( [id] => 9091886 [patent_doc_number] => 20130271197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-17 [patent_title] => 'POWER DROOP REDUCTION VIA CLOCK-GATING FOR AT-SPEED SCAN TESTING' [patent_app_type] => utility [patent_app_number] => 13/444782 [patent_app_country] => US [patent_app_date] => 2012-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5936 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13444782 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/444782
POWER DROOP REDUCTION VIA CLOCK-GATING FOR AT-SPEED SCAN TESTING Apr 10, 2012 Abandoned
Array ( [id] => 9071187 [patent_doc_number] => 20130262943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'OPTIMIZED SYNCHRONOUS SCAN FLIP FLOP CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/432004 [patent_app_country] => US [patent_app_date] => 2012-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3205 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13432004 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/432004
Optimized synchronous scan flip flop circuit Mar 27, 2012 Issued
Array ( [id] => 8443514 [patent_doc_number] => 20120260130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-11 [patent_title] => 'NON-VOLATILE RANDOM ACCESS MEMORY TEST SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/430793 [patent_app_country] => US [patent_app_date] => 2012-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2530 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13430793 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/430793
NON-VOLATILE RANDOM ACCESS MEMORY TEST SYSTEM AND METHOD Mar 26, 2012 Abandoned
Array ( [id] => 8432788 [patent_doc_number] => 20120254663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-04 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND INFORMATION PROCESSING APPARATUS INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/430766 [patent_app_country] => US [patent_app_date] => 2012-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9816 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13430766 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/430766
Semiconductor memory device and information processing apparatus including the same Mar 26, 2012 Issued
Array ( [id] => 8455098 [patent_doc_number] => 20120266044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'NETWORK-CODING-BASED DISTRIBUTED FILE SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/431553 [patent_app_country] => US [patent_app_date] => 2012-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7767 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13431553 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/431553
NETWORK-CODING-BASED DISTRIBUTED FILE SYSTEM Mar 26, 2012 Abandoned
Array ( [id] => 9071186 [patent_doc_number] => 20130262942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'FLASH MEMORY LIFETIME EVALUATION METHOD' [patent_app_type] => utility [patent_app_number] => 13/431336 [patent_app_country] => US [patent_app_date] => 2012-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2937 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13431336 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/431336
FLASH MEMORY LIFETIME EVALUATION METHOD Mar 26, 2012 Abandoned
Array ( [id] => 10098799 [patent_doc_number] => 09135111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'Nonvolatile memory device and bad area managing method thereof' [patent_app_type] => utility [patent_app_number] => 13/431426 [patent_app_country] => US [patent_app_date] => 2012-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 16273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13431426 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/431426
Nonvolatile memory device and bad area managing method thereof Mar 26, 2012 Issued
Array ( [id] => 9847769 [patent_doc_number] => 08949703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-03 [patent_title] => 'Parallel encoding for non-binary linear block code' [patent_app_type] => utility [patent_app_number] => 13/430222 [patent_app_country] => US [patent_app_date] => 2012-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8975 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13430222 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/430222
Parallel encoding for non-binary linear block code Mar 25, 2012 Issued
Array ( [id] => 9879060 [patent_doc_number] => 08966355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Apparatus and method for comparing pairs of binary words' [patent_app_type] => utility [patent_app_number] => 13/430147 [patent_app_country] => US [patent_app_date] => 2012-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 10640 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13430147 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/430147
Apparatus and method for comparing pairs of binary words Mar 25, 2012 Issued
Array ( [id] => 8588731 [patent_doc_number] => 20130007552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'DATA PROCESSING DEVICES, COMPUTER READABLE STORAGE MEDIA, AND METHODS' [patent_app_type] => utility [patent_app_number] => 13/430286 [patent_app_country] => US [patent_app_date] => 2012-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7373 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13430286 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/430286
Data processing devices, computer readable storage media, and methods Mar 25, 2012 Issued
Array ( [id] => 9563892 [patent_doc_number] => 20140181605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'ASYNCHRONOUS PROGRAMMABLE JTAG-BASED INTERFACE TO DEBUG ANY SYSTEM-ON-CHIP STATES, POWER MODES, RESETS, CLOCKS, AND COMPLEX DIGITAL LOGIC' [patent_app_type] => utility [patent_app_number] => 13/997235 [patent_app_country] => US [patent_app_date] => 2012-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5828 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13997235 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/997235
Asynchronous programmable JTAG-based interface to debug any system-on-chip states, power modes, resets, clocks, and complex digital logic Mar 24, 2012 Issued
Array ( [id] => 10834758 [patent_doc_number] => 08862952 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-14 [patent_title] => 'Prioritized memory scanning for data storage systems' [patent_app_type] => utility [patent_app_number] => 13/422509 [patent_app_country] => US [patent_app_date] => 2012-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5389 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13422509 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/422509
Prioritized memory scanning for data storage systems Mar 15, 2012 Issued
Menu