Search

John J. Tabone Jr.

Examiner (ID: 18928, Phone: (571)272-3827 , Office: P/2117 )

Most Active Art Unit
2111
Art Unit(s)
2117, 2111, 2138, 2133
Total Applications
1407
Issued Applications
1231
Pending Applications
47
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10139169 [patent_doc_number] => 09172497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-27 [patent_title] => 'Data processing device and data processing method' [patent_app_type] => utility [patent_app_number] => 13/885557 [patent_app_country] => US [patent_app_date] => 2011-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11646 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13885557 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/885557
Data processing device and data processing method Nov 13, 2011 Issued
Array ( [id] => 9479463 [patent_doc_number] => 20140136927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'ADAPTIVE ECC TECHNIQUES FOR FLASH MEMORY BASED DATA STORAGE' [patent_app_type] => utility [patent_app_number] => 13/879383 [patent_app_country] => US [patent_app_date] => 2011-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10360 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13879383 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/879383
ADAPTIVE ECC TECHNIQUES FOR FLASH MEMORY BASED DATA STORAGE Oct 25, 2011 Abandoned
Array ( [id] => 9297066 [patent_doc_number] => 20140040700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'MULTICORE TYPE ERROR CORRECTION PROCESSING SYSTEM AND ERROR CORRECTION PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/877650 [patent_app_country] => US [patent_app_date] => 2011-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 14428 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13877650 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/877650
Multicore type error correction processing system and error correction processing apparatus Oct 3, 2011 Issued
Array ( [id] => 9077538 [patent_doc_number] => 08555130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Storing encoded data slices in a dispersed storage unit' [patent_app_type] => utility [patent_app_number] => 13/252340 [patent_app_country] => US [patent_app_date] => 2011-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 12188 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13252340 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/252340
Storing encoded data slices in a dispersed storage unit Oct 3, 2011 Issued
Array ( [id] => 8319734 [patent_doc_number] => 08234528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Systems and methods for monitoring a memory system' [patent_app_type] => utility [patent_app_number] => 13/250688 [patent_app_country] => US [patent_app_date] => 2011-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6076 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13250688 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/250688
Systems and methods for monitoring a memory system Sep 29, 2011 Issued
Array ( [id] => 8574836 [patent_doc_number] => 08341498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'System and method of data encoding' [patent_app_type] => utility [patent_app_number] => 13/246521 [patent_app_country] => US [patent_app_date] => 2011-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5793 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13246521 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/246521
System and method of data encoding Sep 26, 2011 Issued
Array ( [id] => 8722709 [patent_doc_number] => 20130073925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-21 [patent_title] => 'ELECTRONIC DEVICE COMPRISING ERROR CORRECTION CODING DEVICE AND ELECTRONIC DEVICE COMPRISING ERROR CORRECTION DECODING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/259743 [patent_app_country] => US [patent_app_date] => 2011-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 21747 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13259743 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/259743
Electronic device comprising error correction coding device and electronic device comprising error correction decoding device Sep 15, 2011 Issued
Array ( [id] => 8395680 [patent_doc_number] => 20120233525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'METHOD FOR OPTIMIZING THE FORWARD ERROR CORRECTION SCHEME' [patent_app_type] => utility [patent_app_number] => 13/230107 [patent_app_country] => US [patent_app_date] => 2011-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3163 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13230107 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/230107
Method for optimizing the forward error correction scheme Sep 11, 2011 Issued
Array ( [id] => 8873035 [patent_doc_number] => 08468423 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-18 [patent_title] => 'Data verification using checksum sidefile' [patent_app_type] => utility [patent_app_number] => 13/224176 [patent_app_country] => US [patent_app_date] => 2011-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5371 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13224176 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/224176
Data verification using checksum sidefile Aug 31, 2011 Issued
Array ( [id] => 8355072 [patent_doc_number] => 08250418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-21 [patent_title] => 'Test mode for parallel load of address dependent data to enable loading of desired data backgrounds' [patent_app_type] => utility [patent_app_number] => 13/214015 [patent_app_country] => US [patent_app_date] => 2011-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5250 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13214015 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/214015
Test mode for parallel load of address dependent data to enable loading of desired data backgrounds Aug 18, 2011 Issued
Array ( [id] => 7569324 [patent_doc_number] => 20110289387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-24 [patent_title] => 'PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL' [patent_app_type] => utility [patent_app_number] => 13/195977 [patent_app_country] => US [patent_app_date] => 2011-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8152 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20110289387.pdf [firstpage_image] =>[orig_patent_app_number] => 13195977 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/195977
Programming error correction code into a solid state memory device with varying bits per cell Aug 1, 2011 Issued
Array ( [id] => 7588650 [patent_doc_number] => 20110283161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'Multi-code LDPC (Low Density Parity Check) decoder' [patent_app_type] => utility [patent_app_number] => 13/191664 [patent_app_country] => US [patent_app_date] => 2011-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13143 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20110283161.pdf [firstpage_image] =>[orig_patent_app_number] => 13191664 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/191664
Multi-code LDPC (low density parity check) decoder Jul 26, 2011 Issued
Array ( [id] => 9012515 [patent_doc_number] => 08527836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'Rank-specific cyclic redundancy check' [patent_app_type] => utility [patent_app_number] => 13/175472 [patent_app_country] => US [patent_app_date] => 2011-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4102 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13175472 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/175472
Rank-specific cyclic redundancy check Jun 30, 2011 Issued
Array ( [id] => 8588727 [patent_doc_number] => 20130007548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'AUTOMATIC TEST-PATTERN GENERATION FOR MEMORY-SHADOW-LOGIC TESTING' [patent_app_type] => utility [patent_app_number] => 13/175530 [patent_app_country] => US [patent_app_date] => 2011-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5432 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13175530 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/175530
Automatic test-pattern generation for memory-shadow-logic testing Jun 30, 2011 Issued
Array ( [id] => 8588739 [patent_doc_number] => 20130007559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'NON-VOLATILE MEMORY ERROR MITIGATION' [patent_app_type] => utility [patent_app_number] => 13/175459 [patent_app_country] => US [patent_app_date] => 2011-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5212 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13175459 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/175459
Non-volatile memory error mitigation Jun 30, 2011 Issued
Array ( [id] => 9431047 [patent_doc_number] => 08707132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-22 [patent_title] => 'Information processing apparatus, information processing method, and storage medium' [patent_app_type] => utility [patent_app_number] => 13/175556 [patent_app_country] => US [patent_app_date] => 2011-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 8008 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13175556 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/175556
Information processing apparatus, information processing method, and storage medium Jun 30, 2011 Issued
Array ( [id] => 9444268 [patent_doc_number] => 08713404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-29 [patent_title] => 'Controller interface providing improved data reliability' [patent_app_type] => utility [patent_app_number] => 13/175610 [patent_app_country] => US [patent_app_date] => 2011-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8177 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13175610 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/175610
Controller interface providing improved data reliability Jun 30, 2011 Issued
Array ( [id] => 9242323 [patent_doc_number] => 08607129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-10 [patent_title] => 'Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic' [patent_app_type] => utility [patent_app_number] => 13/175500 [patent_app_country] => US [patent_app_date] => 2011-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4607 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13175500 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/175500
Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic Jun 30, 2011 Issued
Array ( [id] => 9611710 [patent_doc_number] => 08788898 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-22 [patent_title] => 'Remote testing system' [patent_app_type] => utility [patent_app_number] => 13/153128 [patent_app_country] => US [patent_app_date] => 2011-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6473 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13153128 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/153128
Remote testing system Jun 2, 2011 Issued
Array ( [id] => 9257889 [patent_doc_number] => 08621331 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-12-31 [patent_title] => 'Continuous parallel cyclic BCH decoding architecture' [patent_app_type] => utility [patent_app_number] => 13/152438 [patent_app_country] => US [patent_app_date] => 2011-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4924 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13152438 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/152438
Continuous parallel cyclic BCH decoding architecture Jun 2, 2011 Issued
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