Search

John J. Tabone Jr.

Examiner (ID: 18928, Phone: (571)272-3827 , Office: P/2117 )

Most Active Art Unit
2111
Art Unit(s)
2117, 2111, 2138, 2133
Total Applications
1407
Issued Applications
1231
Pending Applications
47
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6369025 [patent_doc_number] => 20100088562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/635122 [patent_app_country] => US [patent_app_date] => 2009-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11280 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20100088562.pdf [firstpage_image] =>[orig_patent_app_number] => 12635122 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/635122
Functional frequency testing of integrated circuits Dec 9, 2009 Issued
Array ( [id] => 4582036 [patent_doc_number] => 07840863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-23 [patent_title] => 'Functional frequency testing of integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/635068 [patent_app_country] => US [patent_app_date] => 2009-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11204 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/840/07840863.pdf [firstpage_image] =>[orig_patent_app_number] => 12635068 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/635068
Functional frequency testing of integrated circuits Dec 9, 2009 Issued
Array ( [id] => 7493184 [patent_doc_number] => 20110239073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'COMMUNICATION DEVICE AND COMMUNICATION METHOD' [patent_app_type] => utility [patent_app_number] => 13/132693 [patent_app_country] => US [patent_app_date] => 2009-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6147 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20110239073.pdf [firstpage_image] =>[orig_patent_app_number] => 13132693 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/132693
Communication device and communication method Dec 1, 2009 Issued
Array ( [id] => 8366664 [patent_doc_number] => 08255742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Dynamically replicated memory' [patent_app_type] => utility [patent_app_number] => 12/621419 [patent_app_country] => US [patent_app_date] => 2009-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11246 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12621419 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/621419
Dynamically replicated memory Nov 17, 2009 Issued
Array ( [id] => 8693230 [patent_doc_number] => 08392766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Operational method of a controller of a flash memory, and associated memory device and controller thereof' [patent_app_type] => utility [patent_app_number] => 12/619615 [patent_app_country] => US [patent_app_date] => 2009-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3913 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12619615 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/619615
Operational method of a controller of a flash memory, and associated memory device and controller thereof Nov 15, 2009 Issued
Array ( [id] => 8799541 [patent_doc_number] => 08438431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-07 [patent_title] => 'Support element office mode array repair code verification' [patent_app_type] => utility [patent_app_number] => 12/615296 [patent_app_country] => US [patent_app_date] => 2009-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3156 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12615296 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/615296
Support element office mode array repair code verification Nov 9, 2009 Issued
Array ( [id] => 6020562 [patent_doc_number] => 20110225474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'METHOD AND APARATUS FOR ERASURE DECODING AN ECC CODED BITSTREAM' [patent_app_type] => utility [patent_app_number] => 12/998542 [patent_app_country] => US [patent_app_date] => 2009-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4497 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20110225474.pdf [firstpage_image] =>[orig_patent_app_number] => 12998542 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/998542
Method and apparatus for erasure decoding an ECC coded bitstream Oct 27, 2009 Issued
Array ( [id] => 8546468 [patent_doc_number] => 08321771 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-11-27 [patent_title] => 'Modified trace-back using soft output viterbi algorithm (SOVA)' [patent_app_type] => utility [patent_app_number] => 12/572329 [patent_app_country] => US [patent_app_date] => 2009-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12572329 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/572329
Modified trace-back using soft output viterbi algorithm (SOVA) Oct 1, 2009 Issued
Array ( [id] => 8645707 [patent_doc_number] => 08370706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-05 [patent_title] => 'Interleaved correction code transmission' [patent_app_type] => utility [patent_app_number] => 12/572422 [patent_app_country] => US [patent_app_date] => 2009-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6022 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12572422 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/572422
Interleaved correction code transmission Oct 1, 2009 Issued
Array ( [id] => 8220254 [patent_doc_number] => 08195999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Apparatus and method for supporting hybrid automatic repeat request in wireless communication system' [patent_app_type] => utility [patent_app_number] => 12/587067 [patent_app_country] => US [patent_app_date] => 2009-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5404 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/195/08195999.pdf [firstpage_image] =>[orig_patent_app_number] => 12587067 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/587067
Apparatus and method for supporting hybrid automatic repeat request in wireless communication system Sep 30, 2009 Issued
Array ( [id] => 6027849 [patent_doc_number] => 20110080208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-07 [patent_title] => 'LOW POWER DESIGN USING A SCAN BYPASS MULTIPLEXER AS AN ISOLATION CELL' [patent_app_type] => utility [patent_app_number] => 12/571720 [patent_app_country] => US [patent_app_date] => 2009-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5420 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20110080208.pdf [firstpage_image] =>[orig_patent_app_number] => 12571720 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/571720
Low power design using a scan bypass multiplexer as an isolation cell Sep 30, 2009 Issued
Array ( [id] => 7569312 [patent_doc_number] => 20110289375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-24 [patent_title] => 'METHOD FOR CONSTRUCTING AN LDPC CODE, TRANSMITTER, AND RECEIVER' [patent_app_type] => utility [patent_app_number] => 13/121162 [patent_app_country] => US [patent_app_date] => 2009-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7040 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20110289375.pdf [firstpage_image] =>[orig_patent_app_number] => 13121162 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/121162
METHOD FOR CONSTRUCTING AN LDPC CODE, TRANSMITTER, AND RECEIVER Sep 27, 2009 Abandoned
Array ( [id] => 7819944 [patent_doc_number] => 20120066564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'Differential Encoding With Adaptive Resetting' [patent_app_type] => utility [patent_app_number] => 12/806208 [patent_app_country] => US [patent_app_date] => 2009-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3840 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20120066564.pdf [firstpage_image] =>[orig_patent_app_number] => 12806208 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/806208
Differential Encoding With Adaptive Resetting Sep 1, 2009 Abandoned
Array ( [id] => 6073782 [patent_doc_number] => 20110047411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'Handling of errors in a data processing apparatus having a cache storage and a replicated address storage' [patent_app_type] => utility [patent_app_number] => 12/461693 [patent_app_country] => US [patent_app_date] => 2009-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 17802 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20110047411.pdf [firstpage_image] =>[orig_patent_app_number] => 12461693 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/461693
Handling of errors in a data processing apparatus having a cache storage and a replicated address storage Aug 19, 2009 Issued
Array ( [id] => 8552299 [patent_doc_number] => 08327198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-04 [patent_title] => 'On-die logic analyzer for semiconductor die' [patent_app_type] => utility [patent_app_number] => 12/541472 [patent_app_country] => US [patent_app_date] => 2009-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5436 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12541472 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/541472
On-die logic analyzer for semiconductor die Aug 13, 2009 Issued
Array ( [id] => 5932714 [patent_doc_number] => 20110041018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-17 [patent_title] => 'MULTI-MODE PROGRAMMABLE SCAN FLOP' [patent_app_type] => utility [patent_app_number] => 12/540872 [patent_app_country] => US [patent_app_date] => 2009-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8734 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20110041018.pdf [firstpage_image] =>[orig_patent_app_number] => 12540872 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/540872
Multi-mode programmable scan flop Aug 12, 2009 Issued
Array ( [id] => 6605443 [patent_doc_number] => 20100033189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND TEST METHOD USING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/535130 [patent_app_country] => US [patent_app_date] => 2009-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5617 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20100033189.pdf [firstpage_image] =>[orig_patent_app_number] => 12535130 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/535130
SEMICONDUCTOR INTEGRATED CIRCUIT AND TEST METHOD USING THE SAME Aug 3, 2009 Abandoned
Array ( [id] => 6198055 [patent_doc_number] => 20110029813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-03 [patent_title] => 'CIRCUITS AND METHODS FOR PROCESSING MEMORY REDUNDANCY DATA' [patent_app_type] => utility [patent_app_number] => 12/534150 [patent_app_country] => US [patent_app_date] => 2009-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10631 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20110029813.pdf [firstpage_image] =>[orig_patent_app_number] => 12534150 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/534150
Circuits and methods for processing memory redundancy data Aug 1, 2009 Issued
Array ( [id] => 6262984 [patent_doc_number] => 20100031099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'Scan Topology Discovery in Target Systems' [patent_app_type] => utility [patent_app_number] => 12/511957 [patent_app_country] => US [patent_app_date] => 2009-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8158 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20100031099.pdf [firstpage_image] =>[orig_patent_app_number] => 12511957 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/511957
Ascertaining configuration by storing data signals in a topology register Jul 28, 2009 Issued
Array ( [id] => 6565373 [patent_doc_number] => 20100017676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-21 [patent_title] => 'DECODING OF LINEAR CODES WITH PARITY CHECK MATRIX' [patent_app_type] => utility [patent_app_number] => 12/503607 [patent_app_country] => US [patent_app_date] => 2009-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8184 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20100017676.pdf [firstpage_image] =>[orig_patent_app_number] => 12503607 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/503607
Decoding of linear codes with parity check matrix Jul 14, 2009 Issued
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