Search

John James Calvert

Examiner (ID: 2476)

Most Active Art Unit
2407
Art Unit(s)
2899, 2407, 3765, 3408, 3741, 3102
Total Applications
1069
Issued Applications
985
Pending Applications
12
Abandoned Applications
72

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17201978 [patent_doc_number] => 20210342073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => METHOD AND DEVICE FOR WRITING STORED DATA INTO STORAGE MEDIUM BASED ON FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 17/375033 [patent_app_country] => US [patent_app_date] => 2021-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17375033 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/375033
Method and device for writing stored data into storage medium based on flash memory Jul 13, 2021 Issued
Array ( [id] => 16439166 [patent_doc_number] => 20200356492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => SECURING MEMORY ACCESSES IN A VIRTUALIZED ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 16/937296 [patent_app_country] => US [patent_app_date] => 2020-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16937296 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/937296
Securing memory accesses in a virtualized environment Jul 22, 2020 Issued
Array ( [id] => 17515451 [patent_doc_number] => 11294599 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-05 [patent_title] => Registers for restricted memory [patent_app_type] => utility [patent_app_number] => 16/891438 [patent_app_country] => US [patent_app_date] => 2020-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14086 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16891438 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/891438
Registers for restricted memory Jun 2, 2020 Issued
Array ( [id] => 17269047 [patent_doc_number] => 11194472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-07 [patent_title] => Techniques to update a trim parameter in nonvolatile memory [patent_app_type] => utility [patent_app_number] => 16/848608 [patent_app_country] => US [patent_app_date] => 2020-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14501 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16848608 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/848608
Techniques to update a trim parameter in nonvolatile memory Apr 13, 2020 Issued
Array ( [id] => 17209372 [patent_doc_number] => 11169744 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Boosting reads of chunks of data [patent_app_type] => utility [patent_app_number] => 16/836679 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5359 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16836679 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/836679
Boosting reads of chunks of data Mar 30, 2020 Issued
Array ( [id] => 17283152 [patent_doc_number] => 11200181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Asymmetric-channel memory system [patent_app_type] => utility [patent_app_number] => 16/828570 [patent_app_country] => US [patent_app_date] => 2020-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8731 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16828570 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/828570
Asymmetric-channel memory system Mar 23, 2020 Issued
Array ( [id] => 16600236 [patent_doc_number] => 20210026767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => CONTROLLER, MEMORY SYSTEM, AND OPERATING METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 16/822280 [patent_app_country] => US [patent_app_date] => 2020-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7423 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16822280 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/822280
Controller, memory system, and operating methods thereof Mar 17, 2020 Issued
Array ( [id] => 17083992 [patent_doc_number] => 20210278998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => ARCHITECTURE AND DESIGN OF A STORAGE DEVICE CONTROLLER FOR HYPERSCALE INFRASTRUCTURE [patent_app_type] => utility [patent_app_number] => 16/813449 [patent_app_country] => US [patent_app_date] => 2020-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16813449 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/813449
ARCHITECTURE AND DESIGN OF A STORAGE DEVICE CONTROLLER FOR HYPERSCALE INFRASTRUCTURE Mar 8, 2020 Abandoned
Array ( [id] => 17364842 [patent_doc_number] => 11231863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => Block family-based error avoidance for memory devices [patent_app_type] => utility [patent_app_number] => 16/800221 [patent_app_country] => US [patent_app_date] => 2020-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7902 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16800221 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/800221
Block family-based error avoidance for memory devices Feb 24, 2020 Issued
Array ( [id] => 17325194 [patent_doc_number] => 11216206 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Method of operating data storage device [patent_app_type] => utility [patent_app_number] => 16/780783 [patent_app_country] => US [patent_app_date] => 2020-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6795 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16780783 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/780783
Method of operating data storage device Feb 2, 2020 Issued
Array ( [id] => 15837115 [patent_doc_number] => 20200133840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => DATA PROCESSING METHOD AND APPARATUS, AND FLASH DEVICE [patent_app_type] => utility [patent_app_number] => 16/726843 [patent_app_country] => US [patent_app_date] => 2019-12-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8851 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16726843 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/726843
Data processing method and apparatus, and flash device Dec 24, 2019 Issued
Array ( [id] => 17151131 [patent_doc_number] => 11144208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => Data compression system using base values and methods thereof [patent_app_type] => utility [patent_app_number] => 16/724609 [patent_app_country] => US [patent_app_date] => 2019-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5590 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16724609 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/724609
Data compression system using base values and methods thereof Dec 22, 2019 Issued
Array ( [id] => 15624947 [patent_doc_number] => 20200082878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => CALIBRATION OF OPEN BLOCKS IN NAND FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 16/681899 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8375 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16681899 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/681899
Calibration of open blocks in NAND flash memory Nov 12, 2019 Issued
Array ( [id] => 15714593 [patent_doc_number] => 20200104063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => MEMORY CONTROLLER SYSTEMS WITH NONVOLATILE MEMORY FOR STORING OPERATING PARAMETERS [patent_app_type] => utility [patent_app_number] => 16/585193 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16585193 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/585193
Memory controller systems with nonvolatile memory for storing operating parameters Sep 26, 2019 Issued
Array ( [id] => 16577251 [patent_doc_number] => 20210011652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => DATA STORAGE ACCESS METHOD, DEVICE AND APPARATUS FOR PERSISTENT MEMORY [patent_app_type] => utility [patent_app_number] => 16/553276 [patent_app_country] => US [patent_app_date] => 2019-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8645 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16553276 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/553276
Data storage access method, device and apparatus for persistent memory Aug 27, 2019 Issued
Array ( [id] => 15530835 [patent_doc_number] => 20200057723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-20 [patent_title] => SLOT/SUB-SLOT PREFETCH ARCHITECTURE FOR MULTIPLE MEMORY REQUESTORS [patent_app_type] => utility [patent_app_number] => 16/552418 [patent_app_country] => US [patent_app_date] => 2019-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4948 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16552418 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/552418
Slot/sub-slot prefetch architecture for multiple memory requestors Aug 26, 2019 Issued
Array ( [id] => 16659384 [patent_doc_number] => 20210056021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => LOGICAL-TO-PHYSICAL MAP SYNCHRONIZATION IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/548107 [patent_app_country] => US [patent_app_date] => 2019-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16548107 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/548107
Logical-to-physical map synchronization in a memory device Aug 21, 2019 Issued
Array ( [id] => 16659231 [patent_doc_number] => 20210055868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => PREDICTIVE MEMORY MANAGEMENT [patent_app_type] => utility [patent_app_number] => 16/545372 [patent_app_country] => US [patent_app_date] => 2019-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16545372 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/545372
Predictive memory management Aug 19, 2019 Issued
Array ( [id] => 16584683 [patent_doc_number] => 20210019085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => ARBITER CIRCUIT FOR COMMANDS FROM MULTIPLE PHYSICAL FUNCTIONS IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 16/515699 [patent_app_country] => US [patent_app_date] => 2019-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16515699 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/515699
Arbiter circuit for commands from multiple physical functions in a memory sub-system Jul 17, 2019 Issued
Array ( [id] => 17046578 [patent_doc_number] => 11099758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Memory management of computing devices [patent_app_type] => utility [patent_app_number] => 16/513134 [patent_app_country] => US [patent_app_date] => 2019-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6823 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513134 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513134
Memory management of computing devices Jul 15, 2019 Issued
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