
John K. Ford
Examiner (ID: 11164)
| Most Active Art Unit | 3407 |
| Art Unit(s) | 3753, 3743, 3784, 3744, 3405, 3406, 3407, 2743 |
| Total Applications | 2062 |
| Issued Applications | 1392 |
| Pending Applications | 55 |
| Abandoned Applications | 615 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2790220
[patent_doc_number] => 05130578
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-07-14
[patent_title] => 'Efficient high speed N-word comparator'
[patent_app_type] => 1
[patent_app_number] => 7/444454
[patent_app_country] => US
[patent_app_date] => 1989-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2309
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/130/05130578.pdf
[firstpage_image] =>[orig_patent_app_number] => 444454
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/444454 | Efficient high speed N-word comparator | Nov 29, 1989 | Issued |
Array
(
[id] => 2710212
[patent_doc_number] => 04992674
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-02-12
[patent_title] => 'Controlled slew peak detector'
[patent_app_type] => 1
[patent_app_number] => 7/404156
[patent_app_country] => US
[patent_app_date] => 1989-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 5
[patent_no_of_words] => 2713
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/992/04992674.pdf
[firstpage_image] =>[orig_patent_app_number] => 404156
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/404156 | Controlled slew peak detector | Sep 6, 1989 | Issued |
Array
(
[id] => 2673896
[patent_doc_number] => 05047662
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-09-10
[patent_title] => 'Inductive load driving circuit with inductively induced voltage compensating means'
[patent_app_type] => 1
[patent_app_number] => 7/399147
[patent_app_country] => US
[patent_app_date] => 1989-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2868
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/047/05047662.pdf
[firstpage_image] =>[orig_patent_app_number] => 399147
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/399147 | Inductive load driving circuit with inductively induced voltage compensating means | Aug 27, 1989 | Issued |
| 07/398857 | SWITCHING CIRCUIT AND DISPLAY DEVICE USING SAME | Aug 24, 1989 | Abandoned |
Array
(
[id] => 2760188
[patent_doc_number] => 05043608
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-08-27
[patent_title] => 'Avalanche photodiode non-linearity cancellation'
[patent_app_type] => 1
[patent_app_number] => 7/397829
[patent_app_country] => US
[patent_app_date] => 1989-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 1224
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/043/05043608.pdf
[firstpage_image] =>[orig_patent_app_number] => 397829
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/397829 | Avalanche photodiode non-linearity cancellation | Aug 23, 1989 | Issued |
Array
(
[id] => 2767392
[patent_doc_number] => 04994694
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-02-19
[patent_title] => 'Complementary composite PNP transistor'
[patent_app_type] => 1
[patent_app_number] => 7/397213
[patent_app_country] => US
[patent_app_date] => 1989-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 1063
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/994/04994694.pdf
[firstpage_image] =>[orig_patent_app_number] => 397213
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/397213 | Complementary composite PNP transistor | Aug 22, 1989 | Issued |
| 07/396636 | SWITCHING CIRCUIT EMPLOYING ELECTRONIC DEVICES IN SERIES WITH AN INDUCTOR TO AVOID COMMUTATION BREAKDOWN | Aug 21, 1989 | Abandoned |
Array
(
[id] => 2739738
[patent_doc_number] => 05077494
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-12-31
[patent_title] => 'Wide temperature range MESFET logic circuit'
[patent_app_type] => 1
[patent_app_number] => 7/396536
[patent_app_country] => US
[patent_app_date] => 1989-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 4222
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/077/05077494.pdf
[firstpage_image] =>[orig_patent_app_number] => 396536
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/396536 | Wide temperature range MESFET logic circuit | Aug 20, 1989 | Issued |
Array
(
[id] => 2760058
[patent_doc_number] => 05043601
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-08-27
[patent_title] => 'Wide-band amplifier useful for squarewave signals'
[patent_app_type] => 1
[patent_app_number] => 7/395130
[patent_app_country] => US
[patent_app_date] => 1989-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1979
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/043/05043601.pdf
[firstpage_image] =>[orig_patent_app_number] => 395130
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/395130 | Wide-band amplifier useful for squarewave signals | Aug 16, 1989 | Issued |
Array
(
[id] => 2685759
[patent_doc_number] => 05045714
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-09-03
[patent_title] => 'Multiplexer with improved channel select circuitry'
[patent_app_type] => 1
[patent_app_number] => 7/393652
[patent_app_country] => US
[patent_app_date] => 1989-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2894
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 291
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/045/05045714.pdf
[firstpage_image] =>[orig_patent_app_number] => 393652
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/393652 | Multiplexer with improved channel select circuitry | Aug 13, 1989 | Issued |
Array
(
[id] => 2622560
[patent_doc_number] => 04968903
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-11-06
[patent_title] => 'Combinational static CMOS logic circuit'
[patent_app_type] => 1
[patent_app_number] => 7/389202
[patent_app_country] => US
[patent_app_date] => 1989-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 2513
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 318
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/968/04968903.pdf
[firstpage_image] =>[orig_patent_app_number] => 389202
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/389202 | Combinational static CMOS logic circuit | Aug 2, 1989 | Issued |
Array
(
[id] => 2736826
[patent_doc_number] => 05032742
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-16
[patent_title] => 'ESD circuit for input which exceeds power supplies in normal operation'
[patent_app_type] => 1
[patent_app_number] => 7/387467
[patent_app_country] => US
[patent_app_date] => 1989-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 7877
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/032/05032742.pdf
[firstpage_image] =>[orig_patent_app_number] => 387467
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/387467 | ESD circuit for input which exceeds power supplies in normal operation | Jul 27, 1989 | Issued |
| 07/382384 | AN OUTPUT CIRCUIT FOR OBTAINING STABLE RISING AND FALLING CHARACTERISTICS | Jul 19, 1989 | Abandoned |
Array
(
[id] => 2740432
[patent_doc_number] => 05077529
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-12-31
[patent_title] => 'Wide bandwidth digital phase locked loop with reduced low frequency intrinsic jitter'
[patent_app_type] => 1
[patent_app_number] => 7/382258
[patent_app_country] => US
[patent_app_date] => 1989-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 2751
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 226
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/077/05077529.pdf
[firstpage_image] =>[orig_patent_app_number] => 382258
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/382258 | Wide bandwidth digital phase locked loop with reduced low frequency intrinsic jitter | Jul 18, 1989 | Issued |
Array
(
[id] => 2775052
[patent_doc_number] => 04985648
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-01-15
[patent_title] => 'Switching output circuit with high speed operation and low power consumption'
[patent_app_type] => 1
[patent_app_number] => 7/386356
[patent_app_country] => US
[patent_app_date] => 1989-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 6814
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 262
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/985/04985648.pdf
[firstpage_image] =>[orig_patent_app_number] => 386356
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/386356 | Switching output circuit with high speed operation and low power consumption | Jul 17, 1989 | Issued |
Array
(
[id] => 2699122
[patent_doc_number] => 04996449
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-02-26
[patent_title] => 'Output circuit having high speed operation and low power dissipation'
[patent_app_type] => 1
[patent_app_number] => 7/380335
[patent_app_country] => US
[patent_app_date] => 1989-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 2558
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/996/04996449.pdf
[firstpage_image] =>[orig_patent_app_number] => 380335
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/380335 | Output circuit having high speed operation and low power dissipation | Jul 16, 1989 | Issued |
Array
(
[id] => 2752820
[patent_doc_number] => 05038054
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-08-06
[patent_title] => 'Protected Darlington transistor arrangement'
[patent_app_type] => 1
[patent_app_number] => 7/380064
[patent_app_country] => US
[patent_app_date] => 1989-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2132
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/038/05038054.pdf
[firstpage_image] =>[orig_patent_app_number] => 380064
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/380064 | Protected Darlington transistor arrangement | Jul 13, 1989 | Issued |
Array
(
[id] => 2771455
[patent_doc_number] => 05036233
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-30
[patent_title] => 'Integrated semiconductor circuit having a unidirectional semiconductor component for preventing saturation of bipolar transistors'
[patent_app_type] => 1
[patent_app_number] => 7/382065
[patent_app_country] => US
[patent_app_date] => 1989-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 1870
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/036/05036233.pdf
[firstpage_image] =>[orig_patent_app_number] => 382065
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/382065 | Integrated semiconductor circuit having a unidirectional semiconductor component for preventing saturation of bipolar transistors | Jul 13, 1989 | Issued |
Array
(
[id] => 2636818
[patent_doc_number] => 04977335
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-12-11
[patent_title] => 'Low driving voltage operation logic circuit'
[patent_app_type] => 1
[patent_app_number] => 7/375615
[patent_app_country] => US
[patent_app_date] => 1989-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6188
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/977/04977335.pdf
[firstpage_image] =>[orig_patent_app_number] => 375615
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/375615 | Low driving voltage operation logic circuit | Jul 4, 1989 | Issued |
Array
(
[id] => 2842806
[patent_doc_number] => 05160863
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-11-03
[patent_title] => 'Delay circuit using primarily a transistor\'s parasitic capacitance'
[patent_app_type] => 1
[patent_app_number] => 7/374198
[patent_app_country] => US
[patent_app_date] => 1989-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 5997
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/160/05160863.pdf
[firstpage_image] =>[orig_patent_app_number] => 374198
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/374198 | Delay circuit using primarily a transistor's parasitic capacitance | Jun 29, 1989 | Issued |