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John K. Peng

Examiner (ID: 7095)

Most Active Art Unit
2602
Art Unit(s)
2714, 2602, 2303, 2617
Total Applications
648
Issued Applications
604
Pending Applications
0
Abandoned Applications
44

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7173752 [patent_doc_number] => 20040078459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Switch operation scheduling mechanism with concurrent connection and queue scheduling' [patent_app_type] => new [patent_app_number] => 10/685376 [patent_app_country] => US [patent_app_date] => 2003-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10417 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20040078459.pdf [firstpage_image] =>[orig_patent_app_number] => 10685376 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/685376
Switch operation scheduling mechanism with concurrent connection and queue scheduling Oct 13, 2003 Issued
Array ( [id] => 7426587 [patent_doc_number] => 20040001484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Method and apparatus for implementing alterations on multiple concurrent frames' [patent_app_type] => new [patent_app_number] => 10/180993 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4971 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20040001484.pdf [firstpage_image] =>[orig_patent_app_number] => 10180993 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/180993
Method and apparatus for implementing alterations on multiple concurrent frames Jun 26, 2002 Issued
Array ( [id] => 7602584 [patent_doc_number] => 07236453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-26 [patent_title] => 'High available method for border gateway protocol version 4' [patent_app_type] => utility [patent_app_number] => 10/185809 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2876 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/236/07236453.pdf [firstpage_image] =>[orig_patent_app_number] => 10185809 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/185809
High available method for border gateway protocol version 4 Jun 26, 2002 Issued
Array ( [id] => 6773351 [patent_doc_number] => 20030016689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'Switch fabric with dual port memory emulation scheme' [patent_app_type] => new [patent_app_number] => 10/180279 [patent_app_country] => US [patent_app_date] => 2002-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6213 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20030016689.pdf [firstpage_image] =>[orig_patent_app_number] => 10180279 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/180279
Switch fabric with dual port memory emulation scheme Jun 25, 2002 Abandoned
Array ( [id] => 6035402 [patent_doc_number] => 20020019868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-14 [patent_title] => 'Method of constructing network topology and interface circuit' [patent_app_type] => new [patent_app_number] => 09/968519 [patent_app_country] => US [patent_app_date] => 2001-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5945 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20020019868.pdf [firstpage_image] =>[orig_patent_app_number] => 09968519 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/968519
Method of constructing network topology and interface circuit Oct 1, 2001 Issued
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