| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3423371
[patent_doc_number] => 05479039
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-26
[patent_title] => 'MOS electrostatic discharge protection device and structure'
[patent_app_type] => 1
[patent_app_number] => 8/125967
[patent_app_country] => US
[patent_app_date] => 1993-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => patents/05/479/05479039.pdf
[firstpage_image] =>[orig_patent_app_number] => 125967
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/125967 | MOS electrostatic discharge protection device and structure | Sep 22, 1993 | Issued |
Array
(
[id] => 3882686
[patent_doc_number] => 05747862
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Spin-polarized electron emitter having semiconductor opto-electronic layer with split valence band and reflecting mirror'
[patent_app_type] => 1
[patent_app_number] => 8/124624
[patent_app_country] => US
[patent_app_date] => 1993-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 24
[patent_no_of_words] => 11176
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/747/05747862.pdf
[firstpage_image] =>[orig_patent_app_number] => 124624
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/124624 | Spin-polarized electron emitter having semiconductor opto-electronic layer with split valence band and reflecting mirror | Sep 21, 1993 | Issued |
| 08/123919 | SINGLE LAYER POLYSILICON EEPROM | Sep 19, 1993 | Abandoned |
Array
(
[id] => 3480224
[patent_doc_number] => 05432381
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-07-11
[patent_title] => 'Manufacturing method for a self-aligned through hole and semiconductor structure'
[patent_app_type] => 1
[patent_app_number] => 8/122302
[patent_app_country] => US
[patent_app_date] => 1993-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_no_of_words] => 2340
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[patent_words_short_claim] => 191
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/432/05432381.pdf
[firstpage_image] =>[orig_patent_app_number] => 122302
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/122302 | Manufacturing method for a self-aligned through hole and semiconductor structure | Sep 16, 1993 | Issued |
Array
(
[id] => 3423260
[patent_doc_number] => 05479031
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-26
[patent_title] => 'Four layer overvoltage protection device having buried regions aligned with shorting dots to increase the accuracy of overshoot voltage value'
[patent_app_type] => 1
[patent_app_number] => 8/119812
[patent_app_country] => US
[patent_app_date] => 1993-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 5455
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/479/05479031.pdf
[firstpage_image] =>[orig_patent_app_number] => 119812
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/119812 | Four layer overvoltage protection device having buried regions aligned with shorting dots to increase the accuracy of overshoot voltage value | Sep 9, 1993 | Issued |
| 08/112139 | SOLID-STATE IMAGING DEVICE CAPABLE OF REMOVING INFLUENCE BY FALSE SIGNALS | Aug 25, 1993 | Abandoned |
| 08/112009 | REDUCING EXTRINSIC BASE-COLLECTOR CAPACITANCE | Aug 24, 1993 | Abandoned |
Array
(
[id] => 3124325
[patent_doc_number] => 05381040
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-10
[patent_title] => 'Small geometry contact'
[patent_app_type] => 1
[patent_app_number] => 8/147861
[patent_app_country] => US
[patent_app_date] => 1993-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2769
[patent_no_of_claims] => 17
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[patent_words_short_claim] => 300
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/381/05381040.pdf
[firstpage_image] =>[orig_patent_app_number] => 147861
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/147861 | Small geometry contact | Aug 23, 1993 | Issued |
Array
(
[id] => 3117790
[patent_doc_number] => 05396086
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-07
[patent_title] => 'LED spacer assembly'
[patent_app_type] => 1
[patent_app_number] => 8/111049
[patent_app_country] => US
[patent_app_date] => 1993-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/396/05396086.pdf
[firstpage_image] =>[orig_patent_app_number] => 111049
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/111049 | LED spacer assembly | Aug 23, 1993 | Issued |
Array
(
[id] => 3463464
[patent_doc_number] => 05382810
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-17
[patent_title] => 'Optoelectronic component'
[patent_app_type] => 1
[patent_app_number] => 8/104127
[patent_app_country] => US
[patent_app_date] => 1993-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 2940
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/382/05382810.pdf
[firstpage_image] =>[orig_patent_app_number] => 104127
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/104127 | Optoelectronic component | Aug 15, 1993 | Issued |
| 08/107293 | IGBT DEVICE WITH PLATINUM LIFETIME CONTROL AND WIDE BUFFER LAYER | Aug 12, 1993 | Abandoned |
Array
(
[id] => 3525836
[patent_doc_number] => 05489804
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-06
[patent_title] => 'Flexible preformed planar structures for interposing between a chip and a substrate'
[patent_app_type] => 1
[patent_app_number] => 8/106157
[patent_app_country] => US
[patent_app_date] => 1993-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 36
[patent_no_of_words] => 15313
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/489/05489804.pdf
[firstpage_image] =>[orig_patent_app_number] => 106157
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/106157 | Flexible preformed planar structures for interposing between a chip and a substrate | Aug 11, 1993 | Issued |
Array
(
[id] => 3069976
[patent_doc_number] => 05352915
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-10-04
[patent_title] => 'Semiconductor component having two integrated insulated gate field effect devices'
[patent_app_type] => 1
[patent_app_number] => 8/103943
[patent_app_country] => US
[patent_app_date] => 1993-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 6895
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[pdf_file] => patents/05/352/05352915.pdf
[firstpage_image] =>[orig_patent_app_number] => 103943
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/103943 | Semiconductor component having two integrated insulated gate field effect devices | Aug 8, 1993 | Issued |
Array
(
[id] => 3006518
[patent_doc_number] => 05371389
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-12-06
[patent_title] => 'Heterojunction bipolar transistor with base layer having graded bandgap'
[patent_app_type] => 1
[patent_app_number] => 8/101685
[patent_app_country] => US
[patent_app_date] => 1993-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3599
[patent_no_of_claims] => 1
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[patent_words_short_claim] => 184
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/371/05371389.pdf
[firstpage_image] =>[orig_patent_app_number] => 101685
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/101685 | Heterojunction bipolar transistor with base layer having graded bandgap | Aug 3, 1993 | Issued |
| 08/098925 | INTERCONNECTION STRUCTURE FOR CONDUCTIVE LAYERS AND METHOD OF FORMATION | Jul 28, 1993 | Pending |
| 08/096917 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF | Jul 25, 1993 | Pending |
Array
(
[id] => 3460757
[patent_doc_number] => 05401989
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-28
[patent_title] => 'Semiconductor device having a basic cell region and an I/O cell region defined on a surface thereof'
[patent_app_type] => 1
[patent_app_number] => 8/086299
[patent_app_country] => US
[patent_app_date] => 1993-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/05/401/05401989.pdf
[firstpage_image] =>[orig_patent_app_number] => 086299
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/086299 | Semiconductor device having a basic cell region and an I/O cell region defined on a surface thereof | Jul 5, 1993 | Issued |
Array
(
[id] => 3579463
[patent_doc_number] => 05523587
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-04
[patent_title] => 'Method for low temperature growth of epitaxial silicon and devices produced thereby'
[patent_app_type] => 1
[patent_app_number] => 8/082194
[patent_app_country] => US
[patent_app_date] => 1993-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/05/523/05523587.pdf
[firstpage_image] =>[orig_patent_app_number] => 082194
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/082194 | Method for low temperature growth of epitaxial silicon and devices produced thereby | Jun 23, 1993 | Issued |
| 08/072551 | SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR FILM OF LOW OXYGEN CONCENTRATION | Jun 6, 1993 | Pending |
Array
(
[id] => 3431235
[patent_doc_number] => 05404039
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-04
[patent_title] => 'Solid state imaging device and method of manufacture therefor'
[patent_app_type] => 1
[patent_app_number] => 8/072599
[patent_app_country] => US
[patent_app_date] => 1993-06-03
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/404/05404039.pdf
[firstpage_image] =>[orig_patent_app_number] => 072599
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/072599 | Solid state imaging device and method of manufacture therefor | Jun 2, 1993 | Issued |