| Application number | Title of the application | Filing Date | Status |
|---|
| 08/033721 | SEMICONDUCTOR MEMORY DEVICE WITH A TRENCH CAPACITOR | Mar 17, 1993 | Pending |
| 08/025749 | PROTECTION CIRCUIT DEVICE FOR A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE | Mar 2, 1993 | Abandoned |
| 08/020459 | POWER-SUPPLY LINES USED IN A UNIT FUNCTIONAL BLOCK | Feb 21, 1993 | Abandoned |
| 08/021747 | SEMICONDUCTOR DEVICE HAVING AN IMPROVED LOW RESISTIVE CONTACT | Feb 18, 1993 | Abandoned |
| 08/011380 | SOLID-STATE IMAGE PICKUP DEVICE AND MANUFACTURING METHOD OF THE SAME | Jan 28, 1993 | Abandoned |
Array
(
[id] => 3103774
[patent_doc_number] => 05315135
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-24
[patent_title] => 'Semiconductor device having I.sup.2 L gate with heterojunction'
[patent_app_type] => 1
[patent_app_number] => 8/007841
[patent_app_country] => US
[patent_app_date] => 1993-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 8
[patent_no_of_words] => 2168
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/315/05315135.pdf
[firstpage_image] =>[orig_patent_app_number] => 007841
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/007841 | Semiconductor device having I.sup.2 L gate with heterojunction | Jan 21, 1993 | Issued |
Array
(
[id] => 3120964
[patent_doc_number] => 05449945
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-09-12
[patent_title] => 'Silicon metal-semiconductor-metal photodetector'
[patent_app_type] => 1
[patent_app_number] => 8/004803
[patent_app_country] => US
[patent_app_date] => 1993-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2979
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/449/05449945.pdf
[firstpage_image] =>[orig_patent_app_number] => 004803
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/004803 | Silicon metal-semiconductor-metal photodetector | Jan 14, 1993 | Issued |
Array
(
[id] => 3836562
[patent_doc_number] => 05712496
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-27
[patent_title] => 'MOS Poly-Si thin film transistor with a flattened channel interface and method of producing same'
[patent_app_type] => 1
[patent_app_number] => 8/002400
[patent_app_country] => US
[patent_app_date] => 1993-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 28
[patent_no_of_words] => 8120
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/712/05712496.pdf
[firstpage_image] =>[orig_patent_app_number] => 002400
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/002400 | MOS Poly-Si thin film transistor with a flattened channel interface and method of producing same | Jan 12, 1993 | Issued |
Array
(
[id] => 3009546
[patent_doc_number] => 05374845
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-12-20
[patent_title] => 'Process for reduced emitter-base capacitance in bipolar transistor'
[patent_app_type] => 1
[patent_app_number] => 7/984384
[patent_app_country] => US
[patent_app_date] => 1992-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 19
[patent_no_of_words] => 6983
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/374/05374845.pdf
[firstpage_image] =>[orig_patent_app_number] => 984384
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/984384 | Process for reduced emitter-base capacitance in bipolar transistor | Dec 1, 1992 | Issued |
| 07/980859 | SRAM CELL WITH BALANCED LOAD RESISTORS | Nov 23, 1992 | Abandoned |
Array
(
[id] => 3521334
[patent_doc_number] => 05506421
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-09
[patent_title] => 'Power MOSFET in silicon carbide'
[patent_app_type] => 1
[patent_app_number] => 7/980753
[patent_app_country] => US
[patent_app_date] => 1992-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 5287
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/506/05506421.pdf
[firstpage_image] =>[orig_patent_app_number] => 980753
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/980753 | Power MOSFET in silicon carbide | Nov 23, 1992 | Issued |
| 07/960880 | A MEMORY APPARATUS WHICH HAS A SILICON NITRIDE FILM WHICH COVERS PERIPHERAL PORTIONS OF A SUBSTRATE AND DOES NOT COVER THE TRANSISTOR AND CAPACITOR PORTION | Oct 13, 1992 | Abandoned |
Array
(
[id] => 3079998
[patent_doc_number] => 05323032
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-06-21
[patent_title] => 'Dual layer epitaxtial base heterojunction bipolar transistor'
[patent_app_type] => 1
[patent_app_number] => 7/941723
[patent_app_country] => US
[patent_app_date] => 1992-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 19
[patent_no_of_words] => 5237
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 26
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/323/05323032.pdf
[firstpage_image] =>[orig_patent_app_number] => 941723
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/941723 | Dual layer epitaxtial base heterojunction bipolar transistor | Sep 7, 1992 | Issued |
| 07/940131 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF | Sep 2, 1992 | Abandoned |
Array
(
[id] => 3024784
[patent_doc_number] => 05326992
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-05
[patent_title] => 'Silicon carbide and SiCAlN heterojunction bipolar transistor structures'
[patent_app_type] => 1
[patent_app_number] => 7/921151
[patent_app_country] => US
[patent_app_date] => 1992-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 6
[patent_no_of_words] => 6900
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/326/05326992.pdf
[firstpage_image] =>[orig_patent_app_number] => 921151
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/921151 | Silicon carbide and SiCAlN heterojunction bipolar transistor structures | Jul 28, 1992 | Issued |
Array
(
[id] => 3012460
[patent_doc_number] => 05355010
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-10-11
[patent_title] => 'Semiconductor device with a dual type polycide layer comprising a uniformly p-type doped silicide'
[patent_app_type] => 1
[patent_app_number] => 7/900993
[patent_app_country] => US
[patent_app_date] => 1992-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 4984
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/355/05355010.pdf
[firstpage_image] =>[orig_patent_app_number] => 900993
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/900993 | Semiconductor device with a dual type polycide layer comprising a uniformly p-type doped silicide | Jun 17, 1992 | Issued |
| 07/899283 | SEMICONDUCTOR ACCELERATION SENSOR AND METHOD OF FABRICATION THEREOF | Jun 15, 1992 | Abandoned |
Array
(
[id] => 3031793
[patent_doc_number] => 05317186
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-31
[patent_title] => 'Ring crystallization of wafers to prevent thermal shock'
[patent_app_type] => 1
[patent_app_number] => 7/898268
[patent_app_country] => US
[patent_app_date] => 1992-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 1450
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 34
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/317/05317186.pdf
[firstpage_image] =>[orig_patent_app_number] => 898268
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/898268 | Ring crystallization of wafers to prevent thermal shock | Jun 14, 1992 | Issued |
Array
(
[id] => 2967533
[patent_doc_number] => 05264717
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-23
[patent_title] => 'HACT structure with reduced surface state effects'
[patent_app_type] => 1
[patent_app_number] => 7/894141
[patent_app_country] => US
[patent_app_date] => 1992-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2832
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/264/05264717.pdf
[firstpage_image] =>[orig_patent_app_number] => 894141
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/894141 | HACT structure with reduced surface state effects | Jun 3, 1992 | Issued |
| 07/888639 | MEMORY WITH EEPROM CELL HAVING CAPACITIVE EFFECT AND METHOD FOR THE READING OF SUCH A CELL | May 26, 1992 | Abandoned |
