
John L. Goodrow
Examiner (ID: 8581)
| Most Active Art Unit | 1506 |
| Art Unit(s) | 2899, 1506, 1756, 1753, 1795, 1507, 1734, 2852 |
| Total Applications | 3289 |
| Issued Applications | 3094 |
| Pending Applications | 3 |
| Abandoned Applications | 192 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3010241
[patent_doc_number] => 05331117
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-19
[patent_title] => 'Method to improve interlevel dielectric planarization'
[patent_app_type] => 1
[patent_app_number] => 7/974923
[patent_app_country] => US
[patent_app_date] => 1992-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 7
[patent_no_of_words] => 1846
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/331/05331117.pdf
[firstpage_image] =>[orig_patent_app_number] => 974923
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/974923 | Method to improve interlevel dielectric planarization | Nov 11, 1992 | Issued |
| 07/968930 | INTERCONNECT STRUCTURE HAVING IMPROVED METALLIZATION | Oct 29, 1992 | Abandoned |
Array
(
[id] => 3023407
[patent_doc_number] => 05288951
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-22
[patent_title] => 'Copper-based metallizations for hybrid integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 7/968810
[patent_app_country] => US
[patent_app_date] => 1992-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2361
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/288/05288951.pdf
[firstpage_image] =>[orig_patent_app_number] => 968810
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/968810 | Copper-based metallizations for hybrid integrated circuits | Oct 29, 1992 | Issued |
Array
(
[id] => 3057027
[patent_doc_number] => 05345040
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-09-06
[patent_title] => 'Device including a conductor truck foil'
[patent_app_type] => 1
[patent_app_number] => 7/967498
[patent_app_country] => US
[patent_app_date] => 1992-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2273
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/345/05345040.pdf
[firstpage_image] =>[orig_patent_app_number] => 967498
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/967498 | Device including a conductor truck foil | Oct 27, 1992 | Issued |
Array
(
[id] => 3430253
[patent_doc_number] => 05403978
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-04
[patent_title] => 'Two-layer or multilayer printed circuit board'
[patent_app_type] => 1
[patent_app_number] => 7/966773
[patent_app_country] => US
[patent_app_date] => 1992-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 14
[patent_no_of_words] => 5996
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/403/05403978.pdf
[firstpage_image] =>[orig_patent_app_number] => 966773
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/966773 | Two-layer or multilayer printed circuit board | Oct 26, 1992 | Issued |
Array
(
[id] => 3446410
[patent_doc_number] => 05397861
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-14
[patent_title] => 'Electrical interconnection board'
[patent_app_type] => 1
[patent_app_number] => 7/964346
[patent_app_country] => US
[patent_app_date] => 1992-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 31
[patent_no_of_words] => 1679
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/397/05397861.pdf
[firstpage_image] =>[orig_patent_app_number] => 964346
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/964346 | Electrical interconnection board | Oct 20, 1992 | Issued |
Array
(
[id] => 2888027
[patent_doc_number] => 05268536
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-12-07
[patent_title] => 'Method of connecting a lead of a mounting part with a land of a circuit substrate'
[patent_app_type] => 1
[patent_app_number] => 7/961626
[patent_app_country] => US
[patent_app_date] => 1992-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 1796
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 34
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/268/05268536.pdf
[firstpage_image] =>[orig_patent_app_number] => 961626
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/961626 | Method of connecting a lead of a mounting part with a land of a circuit substrate | Oct 15, 1992 | Issued |
Array
(
[id] => 3048268
[patent_doc_number] => 05286927
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-15
[patent_title] => 'Method of manufacturing circuit board and circuit board itself manufactured by said method'
[patent_app_type] => 1
[patent_app_number] => 7/959618
[patent_app_country] => US
[patent_app_date] => 1992-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 13
[patent_no_of_words] => 10629
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/286/05286927.pdf
[firstpage_image] =>[orig_patent_app_number] => 959618
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/959618 | Method of manufacturing circuit board and circuit board itself manufactured by said method | Oct 12, 1992 | Issued |
Array
(
[id] => 3039674
[patent_doc_number] => 05373110
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-12-13
[patent_title] => 'Multilayer circuit board with repaired I/O pin and process for repairing I/O pin on multilayer circuit board'
[patent_app_type] => 1
[patent_app_number] => 7/958756
[patent_app_country] => US
[patent_app_date] => 1992-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 2631
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/373/05373110.pdf
[firstpage_image] =>[orig_patent_app_number] => 958756
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/958756 | Multilayer circuit board with repaired I/O pin and process for repairing I/O pin on multilayer circuit board | Oct 8, 1992 | Issued |
Array
(
[id] => 3102501
[patent_doc_number] => 05315069
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-24
[patent_title] => 'Electromagnetic radiation reduction technique using grounded conductive traces circumscribing internal planes of printed circuit boards'
[patent_app_type] => 1
[patent_app_number] => 7/955928
[patent_app_country] => US
[patent_app_date] => 1992-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4085
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 313
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/315/05315069.pdf
[firstpage_image] =>[orig_patent_app_number] => 955928
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/955928 | Electromagnetic radiation reduction technique using grounded conductive traces circumscribing internal planes of printed circuit boards | Oct 1, 1992 | Issued |
Array
(
[id] => 3099234
[patent_doc_number] => 05293005
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-08
[patent_title] => 'Electronic device having high-density wiring'
[patent_app_type] => 1
[patent_app_number] => 7/953967
[patent_app_country] => US
[patent_app_date] => 1992-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 7535
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/293/05293005.pdf
[firstpage_image] =>[orig_patent_app_number] => 953967
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/953967 | Electronic device having high-density wiring | Sep 28, 1992 | Issued |
| 07/951072 | MAGNETIC VIAS WITHIN MULTI-LAYER, 3-DIMENSIONAL STRUCTURES/SUBSTRATES | Sep 23, 1992 | Abandoned |
Array
(
[id] => 2940804
[patent_doc_number] => 05260519
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-09
[patent_title] => 'Multilayer ceramic substrate with graded vias'
[patent_app_type] => 1
[patent_app_number] => 7/949595
[patent_app_country] => US
[patent_app_date] => 1992-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 4549
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/260/05260519.pdf
[firstpage_image] =>[orig_patent_app_number] => 949595
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/949595 | Multilayer ceramic substrate with graded vias | Sep 22, 1992 | Issued |
Array
(
[id] => 3108671
[patent_doc_number] => 05293504
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-08
[patent_title] => 'Multilayer ceramic substrate with capped vias'
[patent_app_type] => 1
[patent_app_number] => 7/949598
[patent_app_country] => US
[patent_app_date] => 1992-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 5354
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/293/05293504.pdf
[firstpage_image] =>[orig_patent_app_number] => 949598
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/949598 | Multilayer ceramic substrate with capped vias | Sep 22, 1992 | Issued |
Array
(
[id] => 3096342
[patent_doc_number] => 05290970
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-01
[patent_title] => 'Multilayer printed circuit board rework method and rework pin'
[patent_app_type] => 1
[patent_app_number] => 7/947227
[patent_app_country] => US
[patent_app_date] => 1992-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3804
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/290/05290970.pdf
[firstpage_image] =>[orig_patent_app_number] => 947227
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/947227 | Multilayer printed circuit board rework method and rework pin | Sep 17, 1992 | Issued |
Array
(
[id] => 3078891
[patent_doc_number] => 05322975
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-06-21
[patent_title] => 'Universal carrier supported thin copper line'
[patent_app_type] => 1
[patent_app_number] => 7/947711
[patent_app_country] => US
[patent_app_date] => 1992-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 3305
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 39
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/322/05322975.pdf
[firstpage_image] =>[orig_patent_app_number] => 947711
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/947711 | Universal carrier supported thin copper line | Sep 17, 1992 | Issued |
Array
(
[id] => 3108654
[patent_doc_number] => 05293503
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-08
[patent_title] => 'Semiconductor device having multilayer metal interconnection'
[patent_app_type] => 1
[patent_app_number] => 7/943228
[patent_app_country] => US
[patent_app_date] => 1992-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 2016
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 220
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/293/05293503.pdf
[firstpage_image] =>[orig_patent_app_number] => 943228
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/943228 | Semiconductor device having multilayer metal interconnection | Sep 9, 1992 | Issued |
Array
(
[id] => 3013629
[patent_doc_number] => 05276290
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-04
[patent_title] => 'Electroplating process and composition'
[patent_app_type] => 1
[patent_app_number] => 7/943067
[patent_app_country] => US
[patent_app_date] => 1992-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 5326
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/276/05276290.pdf
[firstpage_image] =>[orig_patent_app_number] => 943067
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/943067 | Electroplating process and composition | Sep 9, 1992 | Issued |
Array
(
[id] => 2940768
[patent_doc_number] => 05260517
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-09
[patent_title] => 'Interconnect lead with stress joint'
[patent_app_type] => 1
[patent_app_number] => 7/942951
[patent_app_country] => US
[patent_app_date] => 1992-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2843
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/260/05260517.pdf
[firstpage_image] =>[orig_patent_app_number] => 942951
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/942951 | Interconnect lead with stress joint | Sep 8, 1992 | Issued |
Array
(
[id] => 3058687
[patent_doc_number] => 05357060
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-10-18
[patent_title] => 'Pattern structure of a printed circuit board'
[patent_app_type] => 1
[patent_app_number] => 7/939016
[patent_app_country] => US
[patent_app_date] => 1992-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 1168
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/357/05357060.pdf
[firstpage_image] =>[orig_patent_app_number] => 939016
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/939016 | Pattern structure of a printed circuit board | Sep 1, 1992 | Issued |