
John L. Leguyader
Director (ID: 9832, Phone: (571)272-4650 , Office: P/2600 )
| Most Active Art Unit | 1805 |
| Art Unit(s) | 1635, 1804, 1805, 2899, 1633, 1809, 1621 |
| Total Applications | 501 |
| Issued Applications | 292 |
| Pending Applications | 54 |
| Abandoned Applications | 155 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18696097
[patent_doc_number] => 20230326528
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-12
[patent_title] => READ THRESHOLD CALIBRATION FOR CROSS-TEMPERATURE LONG, SEQUENTIAL READS
[patent_app_type] => utility
[patent_app_number] => 17/714379
[patent_app_country] => US
[patent_app_date] => 2022-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8925
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 14
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17714379
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/714379 | Read threshold calibration for cross-temperature long, sequential reads | Apr 5, 2022 | Issued |
Array
(
[id] => 18679506
[patent_doc_number] => 20230317162
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-05
[patent_title] => DIFFERENTIAL PROGRAMMING OF TWO-TERMINAL MEMORY WITH PROGRAM DETECTION AND MULTI-PATH DISABLEMENT
[patent_app_type] => utility
[patent_app_number] => 17/710858
[patent_app_country] => US
[patent_app_date] => 2022-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22801
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17710858
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/710858 | Differential programming of two-terminal memory with program detection and multi-path disablement | Mar 30, 2022 | Issued |
Array
(
[id] => 17839664
[patent_doc_number] => 20220276969
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-01
[patent_title] => SEDRAM-BASED STACKED CACHE SYSTEM AND DEVICE AND CONTROLLING METHOD THEREFOR
[patent_app_type] => utility
[patent_app_number] => 17/708130
[patent_app_country] => US
[patent_app_date] => 2022-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8779
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17708130
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/708130 | SEDRAM-based stacked cache system and device and controlling method therefor | Mar 29, 2022 | Issued |
Array
(
[id] => 17932973
[patent_doc_number] => 20220328099
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-13
[patent_title] => METHOD AND APPARATUS FOR PERFORMING A MAC OPERATION IN A MEMORY ARRAY
[patent_app_type] => utility
[patent_app_number] => 17/709183
[patent_app_country] => US
[patent_app_date] => 2022-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5684
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17709183
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/709183 | Method and apparatus for performing a MAC operation in a memory array | Mar 29, 2022 | Issued |
Array
(
[id] => 17737753
[patent_doc_number] => 20220223215
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-14
[patent_title] => DEFECT DETECTION DURING PROGRAM VERIFY IN A MEMORY SUB-SYSTEM
[patent_app_type] => utility
[patent_app_number] => 17/707766
[patent_app_country] => US
[patent_app_date] => 2022-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11171
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17707766
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/707766 | Defect detection during program verify in a memory sub-system | Mar 28, 2022 | Issued |
Array
(
[id] => 18615524
[patent_doc_number] => 20230282261
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-07
[patent_title] => SPIN-ORBIT TORQUE MAGNETIC RANDOM ACCESS MEMORY CIRCUIT AND LAYOUT THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/707934
[patent_app_country] => US
[patent_app_date] => 2022-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4956
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17707934
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/707934 | Spin-orbit torque magnetic random access memory circuit and layout thereof | Mar 28, 2022 | Issued |
Array
(
[id] => 20082503
[patent_doc_number] => 12356600
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-08
[patent_title] => SRAM memory cell device comprising ferroelectric access and storage transistors
[patent_app_type] => utility
[patent_app_number] => 17/703931
[patent_app_country] => US
[patent_app_date] => 2022-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 20
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 286
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17703931
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/703931 | SRAM memory cell device comprising ferroelectric access and storage transistors | Mar 23, 2022 | Issued |
Array
(
[id] => 18615523
[patent_doc_number] => 20230282260
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-07
[patent_title] => BOTTOM-PINNED SPIN-ORBIT TORQUE MAGNETIC RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/701703
[patent_app_country] => US
[patent_app_date] => 2022-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5077
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701703
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/701703 | Bottom-pinned spin-orbit torque magnetic random access memory and method of manufacturing the same | Mar 22, 2022 | Issued |
Array
(
[id] => 18967221
[patent_doc_number] => 11900999
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-13
[patent_title] => Memory cycling tracking for threshold voltage variation systems and methods
[patent_app_type] => utility
[patent_app_number] => 17/702562
[patent_app_country] => US
[patent_app_date] => 2022-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 8580
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17702562
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/702562 | Memory cycling tracking for threshold voltage variation systems and methods | Mar 22, 2022 | Issued |
Array
(
[id] => 18937208
[patent_doc_number] => 11889673
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-30
[patent_title] => Dual port SRAM cell and design method thereof
[patent_app_type] => utility
[patent_app_number] => 17/698336
[patent_app_country] => US
[patent_app_date] => 2022-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 13325
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17698336
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/698336 | Dual port SRAM cell and design method thereof | Mar 17, 2022 | Issued |
Array
(
[id] => 19110327
[patent_doc_number] => 11963462
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-16
[patent_title] => Magneto-resistive random access memory magnetic tunnel junction and cell with voltage-controlled writing
[patent_app_type] => utility
[patent_app_number] => 17/698146
[patent_app_country] => US
[patent_app_date] => 2022-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 5327
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17698146
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/698146 | Magneto-resistive random access memory magnetic tunnel junction and cell with voltage-controlled writing | Mar 17, 2022 | Issued |
Array
(
[id] => 18319013
[patent_doc_number] => 20230117141
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-20
[patent_title] => SEMICONDUCTOR DEVICE HAVING A NON-VOLTAILE MEMORY WITH HIGH SPEED-READ OPERATION
[patent_app_type] => utility
[patent_app_number] => 17/696947
[patent_app_country] => US
[patent_app_date] => 2022-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7614
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17696947
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/696947 | Semiconductor device having a non-voltaile memory with high speed-read operation | Mar 16, 2022 | Issued |
Array
(
[id] => 17708274
[patent_doc_number] => 20220208282
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-30
[patent_title] => METHOD OF CONTROLLING A SEMICONDUCTOR MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/696339
[patent_app_country] => US
[patent_app_date] => 2022-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 25043
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17696339
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/696339 | Method of controlling a semiconductor memory including memory cells and a word line | Mar 15, 2022 | Issued |
Array
(
[id] => 18631517
[patent_doc_number] => 20230290419
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-14
[patent_title] => MLC PROGRAMMING TECHNIQUES IN A MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/690713
[patent_app_country] => US
[patent_app_date] => 2022-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13619
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17690713
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/690713 | MLC programming techniques in a memory device | Mar 8, 2022 | Issued |
Array
(
[id] => 18615532
[patent_doc_number] => 20230282269
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-07
[patent_title] => FUSE DEVICE AND OPERATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/686362
[patent_app_country] => US
[patent_app_date] => 2022-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3915
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17686362
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/686362 | Fuse device and operation method thereof | Mar 2, 2022 | Issued |
Array
(
[id] => 19046479
[patent_doc_number] => 11935598
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-19
[patent_title] => Semiconductor storage device and methods for writing the same
[patent_app_type] => utility
[patent_app_number] => 17/685873
[patent_app_country] => US
[patent_app_date] => 2022-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 22
[patent_no_of_words] => 11788
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17685873
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/685873 | Semiconductor storage device and methods for writing the same | Mar 2, 2022 | Issued |
Array
(
[id] => 18615533
[patent_doc_number] => 20230282270
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-07
[patent_title] => PARALLEL ACCESS IN A MEMORY ARRAY
[patent_app_type] => utility
[patent_app_number] => 17/686240
[patent_app_country] => US
[patent_app_date] => 2022-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18436
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17686240
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/686240 | Parallel access in a memory array | Mar 2, 2022 | Issued |
Array
(
[id] => 18268960
[patent_doc_number] => 20230090202
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-23
[patent_title] => MEMORY DEVICE AND MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 17/686148
[patent_app_country] => US
[patent_app_date] => 2022-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 25710
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17686148
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/686148 | Memory device configured to apply different erase intensities to different blocks during an erase operation and memory system for instructing the memory device to carry out the erase operation | Mar 2, 2022 | Issued |
Array
(
[id] => 19540806
[patent_doc_number] => 12133372
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-29
[patent_title] => Pumping capacitor and semiconductor memory device including the same
[patent_app_type] => utility
[patent_app_number] => 17/683562
[patent_app_country] => US
[patent_app_date] => 2022-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 9178
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17683562
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/683562 | Pumping capacitor and semiconductor memory device including the same | Feb 28, 2022 | Issued |
Array
(
[id] => 18599984
[patent_doc_number] => 20230274785
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-31
[patent_title] => SELECTIVE INHIBIT BITLINE VOLTAGE TO CELLS WITH WORSE PROGRAM DISTURB
[patent_app_type] => utility
[patent_app_number] => 17/682280
[patent_app_country] => US
[patent_app_date] => 2022-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12291
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17682280
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/682280 | Selective inhibit bitline voltage to cells with worse program disturb | Feb 27, 2022 | Issued |