Search

John L. Leguyader

Director (ID: 9832, Phone: (571)272-4650 , Office: P/2600 )

Most Active Art Unit
1805
Art Unit(s)
1635, 1804, 1805, 2899, 1633, 1809, 1621
Total Applications
501
Issued Applications
292
Pending Applications
54
Abandoned Applications
155

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20019328 [patent_doc_number] => 20250157550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => Voltage Control in Memory Devices [patent_app_type] => utility [patent_app_number] => 18/399613 [patent_app_country] => US [patent_app_date] => 2023-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1846 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18399613 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/399613
Voltage Control in Memory Devices Dec 27, 2023 Pending
Array ( [id] => 20495191 [patent_doc_number] => 12537067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Method of operating memory, memory, and memory system [patent_app_type] => utility [patent_app_number] => 18/542128 [patent_app_country] => US [patent_app_date] => 2023-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3681 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18542128 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/542128
Method of operating memory, memory, and memory system Dec 14, 2023 Issued
Array ( [id] => 19335351 [patent_doc_number] => 20240249781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => CLOCK SIGNAL GENERATOR AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/541839 [patent_app_country] => US [patent_app_date] => 2023-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8559 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18541839 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/541839
CLOCK SIGNAL GENERATOR AND METHOD OF OPERATING THE SAME Dec 14, 2023 Pending
Array ( [id] => 19788267 [patent_doc_number] => 20250061946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => MEMORY AND OPERATING METHOD THEREOF, MEMORY SYSTEM AND READABLE STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/540350 [patent_app_country] => US [patent_app_date] => 2023-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12271 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18540350 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/540350
MEMORY AND OPERATING METHOD THEREOF, MEMORY SYSTEM AND READABLE STORAGE MEDIUM Dec 13, 2023 Pending
Array ( [id] => 20482644 [patent_doc_number] => 12531120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Semiconductor storage device with transistors of peripheral circuits on two chips [patent_app_type] => utility [patent_app_number] => 18/538659 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 40 [patent_no_of_words] => 13896 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 383 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18538659 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/538659
Semiconductor storage device with transistors of peripheral circuits on two chips Dec 12, 2023 Issued
Array ( [id] => 19130652 [patent_doc_number] => 20240136005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => SEMICONDUCTOR DEVICE AND VOLTAGE APPLICATION METHOD [patent_app_type] => utility [patent_app_number] => 18/534498 [patent_app_country] => US [patent_app_date] => 2023-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18534498 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/534498
SEMICONDUCTOR DEVICE AND VOLTAGE APPLICATION METHOD Dec 7, 2023 Pending
Array ( [id] => 19130652 [patent_doc_number] => 20240136005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => SEMICONDUCTOR DEVICE AND VOLTAGE APPLICATION METHOD [patent_app_type] => utility [patent_app_number] => 18/534498 [patent_app_country] => US [patent_app_date] => 2023-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18534498 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/534498
SEMICONDUCTOR DEVICE AND VOLTAGE APPLICATION METHOD Dec 7, 2023 Pending
Array ( [id] => 19237076 [patent_doc_number] => 20240194271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => CONTROL METHOD FOR NAND FLASH MEMORY TO COMPLETE XNOR OPERATION [patent_app_type] => utility [patent_app_number] => 18/532526 [patent_app_country] => US [patent_app_date] => 2023-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18532526 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/532526
Control method for NAND flash memory to complete XNOR operation Dec 6, 2023 Issued
Array ( [id] => 19802633 [patent_doc_number] => 20250068558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => METHOD FOR OPERATING A MEMORY, A MEMORY AND A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/528214 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18528214 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/528214
METHOD FOR OPERATING A MEMORY, A MEMORY AND A MEMORY SYSTEM Dec 3, 2023 Pending
Array ( [id] => 19726909 [patent_doc_number] => 20250029660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => PROGRAMMING METHOD OF A MEMORY, MEMORY AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/528126 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9418 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18528126 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/528126
PROGRAMMING METHOD OF A MEMORY, MEMORY AND MEMORY SYSTEM Dec 3, 2023 Pending
Array ( [id] => 19820726 [patent_doc_number] => 20250078933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => MEMORY, OPERATION METHOD OF MEMORY AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/528376 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9830 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18528376 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/528376
MEMORY, OPERATION METHOD OF MEMORY AND MEMORY SYSTEM Dec 3, 2023 Pending
Array ( [id] => 19237084 [patent_doc_number] => 20240194279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => MANAGING ASYNCHRONOUS POWER LOSS IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/524721 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18524721 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/524721
MANAGING ASYNCHRONOUS POWER LOSS IN A MEMORY DEVICE Nov 29, 2023 Pending
Array ( [id] => 20564854 [patent_doc_number] => 12567468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Pass voltage adjustment for program operation in a memory device with a defective deck [patent_app_type] => utility [patent_app_number] => 18/524694 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8474 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18524694 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/524694
Pass voltage adjustment for program operation in a memory device with a defective deck Nov 29, 2023 Issued
Array ( [id] => 19610795 [patent_doc_number] => 12159675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Nonvolatile memory device including a logic circuit to control word line voltages [patent_app_type] => utility [patent_app_number] => 18/522829 [patent_app_country] => US [patent_app_date] => 2023-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 12646 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18522829 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/522829
Nonvolatile memory device including a logic circuit to control word line voltages Nov 28, 2023 Issued
Array ( [id] => 20636595 [patent_doc_number] => 12597476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-07 [patent_title] => Program verify compensation in a memory device with a defective deck [patent_app_type] => utility [patent_app_number] => 18/521957 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 10504 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18521957 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/521957
PROGRAM VERIFY COMPENSATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK Nov 27, 2023 Issued
Array ( [id] => 20581203 [patent_doc_number] => 12573457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Non-volatile memory device and operating method thereof including a negative discharge voltage [patent_app_type] => utility [patent_app_number] => 18/512746 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4494 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18512746 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/512746
Non-volatile memory device and operating method thereof including a negative discharge voltage Nov 16, 2023 Issued
Array ( [id] => 20274669 [patent_doc_number] => 12444453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Volatile data storage in NAND memory [patent_app_type] => utility [patent_app_number] => 18/388032 [patent_app_country] => US [patent_app_date] => 2023-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 13727 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18388032 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/388032
Volatile data storage in NAND memory Nov 7, 2023 Issued
Array ( [id] => 19237070 [patent_doc_number] => 20240194265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => MEMORY DEVICE HAVING ASYMMETRIC PAGE BUFFER ARRAY ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/386472 [patent_app_country] => US [patent_app_date] => 2023-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16950 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18386472 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/386472
Memory device having asymmetric page buffer array architecture Nov 1, 2023 Issued
Array ( [id] => 18990868 [patent_doc_number] => 20240062837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => METHOD AND MEMORY USED FOR REDUCING PROGRAM DISTURBANCE BY ADJUSTING VOLTAGE OF DUMMY WORD LINE [patent_app_type] => utility [patent_app_number] => 18/385642 [patent_app_country] => US [patent_app_date] => 2023-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4273 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18385642 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/385642
METHOD AND MEMORY USED FOR REDUCING PROGRAM DISTURBANCE BY ADJUSTING VOLTAGE OF DUMMY WORD LINE Oct 30, 2023 Pending
Array ( [id] => 20596311 [patent_doc_number] => 12580034 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Memory device and method of fabricating memory device including a test circuit [patent_app_type] => utility [patent_app_number] => 18/383603 [patent_app_country] => US [patent_app_date] => 2023-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8157 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18383603 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/383603
Memory device and method of fabricating memory device including a test circuit Oct 24, 2023 Issued
Menu