
John L. Leguyader
Director (ID: 9832, Phone: (571)272-4650 , Office: P/2600 )
| Most Active Art Unit | 1805 |
| Art Unit(s) | 1635, 1804, 1805, 2899, 1633, 1809, 1621 |
| Total Applications | 501 |
| Issued Applications | 292 |
| Pending Applications | 54 |
| Abandoned Applications | 155 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18112668
[patent_doc_number] => 20230005548
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-05
[patent_title] => DATA ERASE OPERATIONS FOR A MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 17/943139
[patent_app_country] => US
[patent_app_date] => 2022-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7505
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17943139
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/943139 | Data erase operations for a memory system | Sep 11, 2022 | Issued |
Array
(
[id] => 19781273
[patent_doc_number] => 12230311
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-18
[patent_title] => Aliased row hammer detector
[patent_app_type] => utility
[patent_app_number] => 17/941655
[patent_app_country] => US
[patent_app_date] => 2022-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 11455
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17941655
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/941655 | Aliased row hammer detector | Sep 8, 2022 | Issued |
Array
(
[id] => 18097044
[patent_doc_number] => 20220415385
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-29
[patent_title] => Wordline Coupling Techniques
[patent_app_type] => utility
[patent_app_number] => 17/897716
[patent_app_country] => US
[patent_app_date] => 2022-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6091
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17897716
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/897716 | Wordline coupling techniques | Aug 28, 2022 | Issued |
Array
(
[id] => 19007411
[patent_doc_number] => 20240071482
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-29
[patent_title] => MIXED BITLINE LOCKOUT FOR QLC/TLC DIE
[patent_app_type] => utility
[patent_app_number] => 17/895304
[patent_app_country] => US
[patent_app_date] => 2022-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20419
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17895304
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/895304 | Mixed bitline lockout for QLC/TLC die | Aug 24, 2022 | Issued |
Array
(
[id] => 19582345
[patent_doc_number] => 12148471
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-11-19
[patent_title] => Reconfigurable computational memory device, operation method of the reconfigurable computational memory device and semiconductor die including the reconfigurable computational memory device
[patent_app_type] => utility
[patent_app_number] => 17/892130
[patent_app_country] => US
[patent_app_date] => 2022-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 8624
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17892130
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/892130 | Reconfigurable computational memory device, operation method of the reconfigurable computational memory device and semiconductor die including the reconfigurable computational memory device | Aug 21, 2022 | Issued |
Array
(
[id] => 18990870
[patent_doc_number] => 20240062839
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-22
[patent_title] => PERFORMING BLOCK-LEVEL MEDIA MANAGEMENT OPERATIONS FOR BLOCK STRIPES IN A MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/892437
[patent_app_country] => US
[patent_app_date] => 2022-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8258
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17892437
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/892437 | Performing block-level media management operations for block stripes in a memory device | Aug 21, 2022 | Issued |
Array
(
[id] => 18990866
[patent_doc_number] => 20240062835
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-22
[patent_title] => ADAPTIVE INTEGRITY SCAN RATES IN A MEMORY SUB-SYSTEM BASED ON BLOCK HEALTH METRICS
[patent_app_type] => utility
[patent_app_number] => 17/891859
[patent_app_country] => US
[patent_app_date] => 2022-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7636
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17891859
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/891859 | Adaptive integrity scan rates in a memory sub-system based on block health metrics | Aug 18, 2022 | Issued |
Array
(
[id] => 19399491
[patent_doc_number] => 12073876
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-27
[patent_title] => Memory clock level-shifting buffer with extended range
[patent_app_type] => utility
[patent_app_number] => 17/891395
[patent_app_country] => US
[patent_app_date] => 2022-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5810
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17891395
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/891395 | Memory clock level-shifting buffer with extended range | Aug 18, 2022 | Issued |
Array
(
[id] => 19494091
[patent_doc_number] => 12112812
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-08
[patent_title] => Non-volatile memory with early dummy word line ramp down after precharge
[patent_app_type] => utility
[patent_app_number] => 17/884929
[patent_app_country] => US
[patent_app_date] => 2022-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 34
[patent_no_of_words] => 21365
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884929
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/884929 | Non-volatile memory with early dummy word line ramp down after precharge | Aug 9, 2022 | Issued |
Array
(
[id] => 18158380
[patent_doc_number] => 20230024971
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-26
[patent_title] => MEMORY DEVICE, SYSTEM AND METHOD OF OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/881231
[patent_app_country] => US
[patent_app_date] => 2022-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7043
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17881231
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/881231 | Memory device with dummy word line, system and method for programming thereof | Aug 3, 2022 | Issued |
Array
(
[id] => 19414522
[patent_doc_number] => 12080356
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-03
[patent_title] => Methods of forming integrated circuit structures for capacitive sense NAND memory
[patent_app_type] => utility
[patent_app_number] => 17/876718
[patent_app_country] => US
[patent_app_date] => 2022-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 44
[patent_figures_cnt] => 59
[patent_no_of_words] => 22419
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876718
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/876718 | Methods of forming integrated circuit structures for capacitive sense NAND memory | Jul 28, 2022 | Issued |
Array
(
[id] => 19523813
[patent_doc_number] => 12125551
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-22
[patent_title] => Structure for multiple sense amplifiers of memory device
[patent_app_type] => utility
[patent_app_number] => 17/874973
[patent_app_country] => US
[patent_app_date] => 2022-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 16
[patent_no_of_words] => 8766
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874973
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/874973 | Structure for multiple sense amplifiers of memory device | Jul 26, 2022 | Issued |
Array
(
[id] => 19507654
[patent_doc_number] => 12119083
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-15
[patent_title] => Drive circuit, method for driving drive circuit, and memory
[patent_app_type] => utility
[patent_app_number] => 17/874813
[patent_app_country] => US
[patent_app_date] => 2022-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 8813
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874813
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/874813 | Drive circuit, method for driving drive circuit, and memory | Jul 26, 2022 | Issued |
Array
(
[id] => 18143539
[patent_doc_number] => 20230017388
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-19
[patent_title] => POWER ARCHITECTURE FOR NON-VOLATILE MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/873850
[patent_app_country] => US
[patent_app_date] => 2022-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12822
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873850
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/873850 | Power architecture for non-volatile memory | Jul 25, 2022 | Issued |
Array
(
[id] => 19781304
[patent_doc_number] => 12230342
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-18
[patent_title] => Memory device, memory system, and read operation method thereof
[patent_app_type] => utility
[patent_app_number] => 17/871422
[patent_app_country] => US
[patent_app_date] => 2022-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 12491
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 312
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17871422
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/871422 | Memory device, memory system, and read operation method thereof | Jul 21, 2022 | Issued |
Array
(
[id] => 18219318
[patent_doc_number] => 11594264
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2023-02-28
[patent_title] => Readout circuit layout structure and method of reading data
[patent_app_type] => utility
[patent_app_number] => 17/813998
[patent_app_country] => US
[patent_app_date] => 2022-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 9432
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 342
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813998
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/813998 | Readout circuit layout structure and method of reading data | Jul 20, 2022 | Issued |
Array
(
[id] => 18926785
[patent_doc_number] => 20240029789
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-25
[patent_title] => MEMORY DIE HAVING A UNIQUE STORAGE CAPACITY
[patent_app_type] => utility
[patent_app_number] => 17/870055
[patent_app_country] => US
[patent_app_date] => 2022-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11518
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -24
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870055
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/870055 | MEMORY DIE HAVING A UNIQUE STORAGE CAPACITY | Jul 20, 2022 | Pending |
Array
(
[id] => 18394559
[patent_doc_number] => 20230162780
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-25
[patent_title] => MITIGATING DUTY CYCLE DISTORTION DEGRADATION DUE TO DEVICE AGING ON HIGH-BANDWIDTH MEMORY INTERFACE
[patent_app_type] => utility
[patent_app_number] => 17/866327
[patent_app_country] => US
[patent_app_date] => 2022-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8299
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17866327
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/866327 | Mitigating duty cycle distortion degradation due to device aging on high-bandwidth memory interface | Jul 14, 2022 | Issued |
Array
(
[id] => 18562743
[patent_doc_number] => 11727993
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-15
[patent_title] => Three dimensional stacked nonvolatile semiconductor memory wherein first through fifth voltages are applied at different timings in a program operation
[patent_app_type] => utility
[patent_app_number] => 17/864674
[patent_app_country] => US
[patent_app_date] => 2022-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 28
[patent_no_of_words] => 9782
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 431
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17864674
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/864674 | Three dimensional stacked nonvolatile semiconductor memory wherein first through fifth voltages are applied at different timings in a program operation | Jul 13, 2022 | Issued |
Array
(
[id] => 19765708
[patent_doc_number] => 12224006
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-11
[patent_title] => High-speed and large-current adjustable pulse circuit, operating circuit and operating method of phase-change memory
[patent_app_type] => utility
[patent_app_number] => 18/031356
[patent_app_country] => US
[patent_app_date] => 2022-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4877
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 441
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18031356
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/031356 | High-speed and large-current adjustable pulse circuit, operating circuit and operating method of phase-change memory | Jul 6, 2022 | Issued |