Search

John L. Leguyader

Director (ID: 9832, Phone: (571)272-4650 , Office: P/2600 )

Most Active Art Unit
1805
Art Unit(s)
1635, 1804, 1805, 2899, 1633, 1809, 1621
Total Applications
501
Issued Applications
292
Pending Applications
54
Abandoned Applications
155

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17948995 [patent_doc_number] => 20220336014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => PHASE-CHANGE MEMORY DEVICE FOR IMPROVING RESISTANCE DRIFT AND DYNAMIC RESISTANCE DRIFT COMPENSATION METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 17/857581 [patent_app_country] => US [patent_app_date] => 2022-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2704 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17857581 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/857581
Phase-change memory device for improving resistance drift and dynamic resistance drift compensation method of the same Jul 4, 2022 Issued
Array ( [id] => 20416656 [patent_doc_number] => 12499946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Reliability improvement through delay between multi-stage programming steps in non-volatile memory structures [patent_app_type] => utility [patent_app_number] => 17/847831 [patent_app_country] => US [patent_app_date] => 2022-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 29 [patent_no_of_words] => 9309 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17847831 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/847831
Reliability improvement through delay between multi-stage programming steps in non-volatile memory structures Jun 22, 2022 Issued
Array ( [id] => 19328597 [patent_doc_number] => 12046286 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-07-23 [patent_title] => Programmable logic computation in memory [patent_app_type] => utility [patent_app_number] => 17/847810 [patent_app_country] => US [patent_app_date] => 2022-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 30 [patent_no_of_words] => 7222 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17847810 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/847810
Programmable logic computation in memory Jun 22, 2022 Issued
Array ( [id] => 19596758 [patent_doc_number] => 12154610 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Semiconductor device and semiconductor system [patent_app_type] => utility [patent_app_number] => 17/847967 [patent_app_country] => US [patent_app_date] => 2022-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7033 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17847967 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/847967
Semiconductor device and semiconductor system Jun 22, 2022 Issued
Array ( [id] => 20258833 [patent_doc_number] => 12431196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Semiconductor memory device and operating method for performing program operation [patent_app_type] => utility [patent_app_number] => 17/844965 [patent_app_country] => US [patent_app_date] => 2022-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8895 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17844965 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/844965
Semiconductor memory device and operating method for performing program operation Jun 20, 2022 Issued
Array ( [id] => 18080737 [patent_doc_number] => 20220406349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/842766 [patent_app_country] => US [patent_app_date] => 2022-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17842766 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/842766
Semiconductor storage device having bit line selection circuit formed in memory cell array Jun 15, 2022 Issued
Array ( [id] => 18464143 [patent_doc_number] => 11688436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Sense amplifier and operating method for non-volatile memory with reduced need on adjusting offset to compensate the mismatch [patent_app_type] => utility [patent_app_number] => 17/829333 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 14068 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17829333 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/829333
Sense amplifier and operating method for non-volatile memory with reduced need on adjusting offset to compensate the mismatch May 30, 2022 Issued
Array ( [id] => 17992983 [patent_doc_number] => 20220359020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/751131 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5572 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751131 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/751131
Reducing programming disturbance in memory devices May 22, 2022 Issued
Array ( [id] => 18757253 [patent_doc_number] => 20230360711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => ONE-TIME PROGRAMMABLE (OTP) MEMORY AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/737259 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17737259 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/737259
One-time programmable (OTP) memory and method of operating the same May 4, 2022 Issued
Array ( [id] => 18320850 [patent_doc_number] => 20230118978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/736226 [patent_app_country] => US [patent_app_date] => 2022-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17736226 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/736226
Semiconductor memory device including active regions for reducing disturbance May 3, 2022 Issued
Array ( [id] => 18488134 [patent_doc_number] => 20230215482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => ELECTRONIC DEVICES AND ELECTRONIC SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/733162 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17733162 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/733162
Electronic devices for performing a post-write operation and electronic systems Apr 28, 2022 Issued
Array ( [id] => 17779870 [patent_doc_number] => 20220246220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => OPERATIONAL MODES FOR REDUCED POWER CONSUMPTION IN A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/726351 [patent_app_country] => US [patent_app_date] => 2022-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17726351 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/726351
Operational modes for reduced power consumption in a memory system Apr 20, 2022 Issued
Array ( [id] => 17992981 [patent_doc_number] => 20220359018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => SEMICONDUCTOR DEVICE AND OPERATION METHOD [patent_app_type] => utility [patent_app_number] => 17/724499 [patent_app_country] => US [patent_app_date] => 2022-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17724499 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/724499
Semiconductor device and operation method having power-on operation Apr 19, 2022 Issued
Array ( [id] => 19540822 [patent_doc_number] => 12133389 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => Semiconductor memory device including pass transistors with variable sizes [patent_app_type] => utility [patent_app_number] => 17/723167 [patent_app_country] => US [patent_app_date] => 2022-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 38 [patent_no_of_words] => 26241 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17723167 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/723167
Semiconductor memory device including pass transistors with variable sizes Apr 17, 2022 Issued
Array ( [id] => 18256436 [patent_doc_number] => 20230083475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM AND METHOD OF CONTROLLING THE SAME [patent_app_type] => utility [patent_app_number] => 17/720843 [patent_app_country] => US [patent_app_date] => 2022-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10323 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17720843 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/720843
Semiconductor memory device with operation limit controller Apr 13, 2022 Issued
Array ( [id] => 17932962 [patent_doc_number] => 20220328088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => SEMICONDUCTOR ELEMENT MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/719646 [patent_app_country] => US [patent_app_date] => 2022-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13735 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 415 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17719646 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/719646
Semiconductor element memory device Apr 12, 2022 Issued
Array ( [id] => 18696062 [patent_doc_number] => 20230326493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => THRESHOLD VOLTAGE VARIATION COMPENSATION IN INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/717657 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12268 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17717657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/717657
Threshold voltage variation compensation in integrated circuits Apr 10, 2022 Issued
Array ( [id] => 19029752 [patent_doc_number] => 11929115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Memory device with SRAM cells assisted by non-volatile memory cells and operation method thereof [patent_app_type] => utility [patent_app_number] => 17/715959 [patent_app_country] => US [patent_app_date] => 2022-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8718 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17715959 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/715959
Memory device with SRAM cells assisted by non-volatile memory cells and operation method thereof Apr 7, 2022 Issued
Array ( [id] => 18696099 [patent_doc_number] => 20230326530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => MEMORY APPARATUS AND METHOD OF OPERATION USING STATE DEPENDENT STROBE TIER SCAN TO REDUCE PEAK ICC [patent_app_type] => utility [patent_app_number] => 17/715647 [patent_app_country] => US [patent_app_date] => 2022-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16512 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17715647 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/715647
Memory apparatus and method of operation using state dependent strobe tier scan to reduce peak ICC Apr 6, 2022 Issued
Array ( [id] => 18735518 [patent_doc_number] => 11804259 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Floating body dram with reduced access energy [patent_app_type] => utility [patent_app_number] => 17/715370 [patent_app_country] => US [patent_app_date] => 2022-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3937 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17715370 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/715370
Floating body dram with reduced access energy Apr 6, 2022 Issued
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