Search

John M. Cooney

Examiner (ID: 16925, Phone: (571)272-1070 , Office: P/1765 )

Most Active Art Unit
1765
Art Unit(s)
1765, 1796, 1207, 1503, 1641, 1711
Total Applications
2598
Issued Applications
1702
Pending Applications
194
Abandoned Applications
728

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18156814 [patent_doc_number] => 11569815 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-31 [patent_title] => High electric-thermal performance and high-power density power module [patent_app_type] => utility [patent_app_number] => 17/071280 [patent_app_country] => US [patent_app_date] => 2020-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4572 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17071280 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/071280
High electric-thermal performance and high-power density power module Oct 14, 2020 Issued
Array ( [id] => 18343437 [patent_doc_number] => 11640921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-02 [patent_title] => Process for fabricating an integrated circuit comprising a phase of forming trenches in a substrate and corresponding integrated circuit [patent_app_type] => utility [patent_app_number] => 17/068112 [patent_app_country] => US [patent_app_date] => 2020-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4554 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17068112 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/068112
Process for fabricating an integrated circuit comprising a phase of forming trenches in a substrate and corresponding integrated circuit Oct 11, 2020 Issued
Array ( [id] => 16781601 [patent_doc_number] => 20210118680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => Method for Manufacturing an III-Nitride Semiconductor Structure [patent_app_type] => utility [patent_app_number] => 17/062192 [patent_app_country] => US [patent_app_date] => 2020-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10066 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17062192 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/062192
Method for manufacturing a vertical power device including an III-nitride semiconductor structure Oct 1, 2020 Issued
Array ( [id] => 17908814 [patent_doc_number] => 11462679 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Magnetoresistive random access memory device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/038779 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 74 [patent_no_of_words] => 15025 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17038779 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/038779
Magnetoresistive random access memory device and method of manufacturing the same Sep 29, 2020 Issued
Array ( [id] => 18157338 [patent_doc_number] => 11570339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Photodiode package structure with shutters, forming method thereof, and wearable device having the same [patent_app_type] => utility [patent_app_number] => 17/037738 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 4270 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17037738 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/037738
Photodiode package structure with shutters, forming method thereof, and wearable device having the same Sep 29, 2020 Issued
Array ( [id] => 17517034 [patent_doc_number] => 11296195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Semiconductor device manufacturing method [patent_app_type] => utility [patent_app_number] => 17/038693 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 5388 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17038693 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/038693
Semiconductor device manufacturing method Sep 29, 2020 Issued
Array ( [id] => 17040734 [patent_doc_number] => 20210257370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/036462 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10530 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036462 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/036462
Semiconductor memory devices including stacked transistors and methods of fabricating the same Sep 28, 2020 Issued
Array ( [id] => 17509260 [patent_doc_number] => 20220102363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/035438 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17766 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17035438 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/035438
Semiconductor device including memory cell and fin arrangements Sep 27, 2020 Issued
Array ( [id] => 16577135 [patent_doc_number] => 20210011536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/034722 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4532 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17034722 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/034722
Electronic device Sep 27, 2020 Issued
Array ( [id] => 16579316 [patent_doc_number] => 20210013717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => Highly Flexible Electrical Distribution Grid Edge Energy Manager and Router [patent_app_type] => utility [patent_app_number] => 17/033016 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22411 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033016 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/033016
Highly flexible electrical distribution grid edge energy manager and router Sep 24, 2020 Issued
Array ( [id] => 17040731 [patent_doc_number] => 20210257367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/029238 [patent_app_country] => US [patent_app_date] => 2020-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17029238 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/029238
Semiconductor memory device including a multi-layer electrode Sep 22, 2020 Issued
Array ( [id] => 16692342 [patent_doc_number] => 20210074821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => EMBEDDED SONOS WITH TRIPLE GATE OXIDE AND MANUFACTURING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 17/026820 [patent_app_country] => US [patent_app_date] => 2020-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12871 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17026820 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/026820
EMBEDDED SONOS WITH TRIPLE GATE OXIDE AND MANUFACTURING METHOD OF THE SAME Sep 20, 2020 Abandoned
Array ( [id] => 17956444 [patent_doc_number] => 11482559 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Optical semiconductor device and method of assembling optical semiconductor device [patent_app_type] => utility [patent_app_number] => 17/025576 [patent_app_country] => US [patent_app_date] => 2020-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 25 [patent_no_of_words] => 12878 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17025576 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/025576
Optical semiconductor device and method of assembling optical semiconductor device Sep 17, 2020 Issued
Array ( [id] => 17145280 [patent_doc_number] => 20210313293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => RF AMPLIFIER DEVICES AND METHODS OF MANUFACTURING [patent_app_type] => utility [patent_app_number] => 17/018762 [patent_app_country] => US [patent_app_date] => 2020-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17018762 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/018762
RF amplifier devices including top side contacts and methods of manufacturing Sep 10, 2020 Issued
Array ( [id] => 18190621 [patent_doc_number] => 11581222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Via in semiconductor device structure [patent_app_type] => utility [patent_app_number] => 17/018356 [patent_app_country] => US [patent_app_date] => 2020-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 7435 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17018356 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/018356
Via in semiconductor device structure Sep 10, 2020 Issued
Array ( [id] => 17730825 [patent_doc_number] => 11387227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Memory device having multiple chips and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/017101 [patent_app_country] => US [patent_app_date] => 2020-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 17558 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17017101 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/017101
Memory device having multiple chips and method for manufacturing the same Sep 9, 2020 Issued
Array ( [id] => 17463841 [patent_doc_number] => 20220077147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => SEMICONDUCTOR STRUCTURE WITH BURIED POWER LINE AND BURIED SIGNAL LINE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/014282 [patent_app_country] => US [patent_app_date] => 2020-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7412 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17014282 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/014282
Semiconductor structure with buried power line and buried signal line and method for manufacturing the same Sep 7, 2020 Issued
Array ( [id] => 16528873 [patent_doc_number] => 20200402954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/007233 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007233 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/007233
Semiconductor device structure with back-side layer to reduce leakage Aug 30, 2020 Issued
Array ( [id] => 17448308 [patent_doc_number] => 20220068813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => Frontside-to-Backside Intermixing Architecture [patent_app_type] => utility [patent_app_number] => 17/006695 [patent_app_country] => US [patent_app_date] => 2020-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17006695 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/006695
Frontside-to-backside intermixing architecture for coupling a frontside network to a backside network Aug 27, 2020 Issued
Array ( [id] => 17448204 [patent_doc_number] => 20220068709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => Low Resistivity Tungsten Film And Method Of Manufacture [patent_app_type] => utility [patent_app_number] => 17/002220 [patent_app_country] => US [patent_app_date] => 2020-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3714 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17002220 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/002220
Low resistivity tungsten film and method of manufacture Aug 24, 2020 Issued
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