Search

John M. Cooney

Examiner (ID: 16925, Phone: (571)272-1070 , Office: P/1765 )

Most Active Art Unit
1765
Art Unit(s)
1765, 1796, 1207, 1503, 1641, 1711
Total Applications
2598
Issued Applications
1702
Pending Applications
194
Abandoned Applications
728

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18143499 [patent_doc_number] => 20230017348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/932817 [patent_app_country] => US [patent_app_date] => 2022-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17932817 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/932817
SEMICONDUCTOR MEMORY DEVICE Sep 15, 2022 Abandoned
Array ( [id] => 18294524 [patent_doc_number] => 20230104210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH REDUNDANCY [patent_app_type] => utility [patent_app_number] => 17/945579 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 79663 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17945579 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/945579
3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH REDUNDANCY Sep 14, 2022 Abandoned
Array ( [id] => 18743345 [patent_doc_number] => 20230352333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => 3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH AT LEAST TWO SINGLE-CRYSTAL LAYERS [patent_app_type] => utility [patent_app_number] => 17/945671 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 79818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17945671 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/945671
3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH AT LEAST TWO SINGLE-CRYSTAL LAYERS Sep 14, 2022 Pending
Array ( [id] => 18081089 [patent_doc_number] => 20220406701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => MICROELECTRONIC ASSEMBLIES HAVING AN INTEGRATED VOLTAGE REGULATOR CHIPLET [patent_app_type] => utility [patent_app_number] => 17/822200 [patent_app_country] => US [patent_app_date] => 2022-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15720 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17822200 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/822200
Microelectronic assemblies having an integrated voltage regulator chiplet Aug 24, 2022 Issued
Array ( [id] => 18321112 [patent_doc_number] => 20230119240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/894645 [patent_app_country] => US [patent_app_date] => 2022-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7537 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17894645 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/894645
Semiconductor device having an insulating sheet and a conductive film, and method of manufacturing the same Aug 23, 2022 Issued
Array ( [id] => 19873708 [patent_doc_number] => 12266578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Chips bonding auxiliary structure [patent_app_type] => utility [patent_app_number] => 17/892326 [patent_app_country] => US [patent_app_date] => 2022-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3851 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17892326 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/892326
Chips bonding auxiliary structure Aug 21, 2022 Issued
Array ( [id] => 19654642 [patent_doc_number] => 12176443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Electronic sensor devices and methods of manufacturing electronic sensor devices [patent_app_type] => utility [patent_app_number] => 17/889161 [patent_app_country] => US [patent_app_date] => 2022-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4210 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17889161 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/889161
Electronic sensor devices and methods of manufacturing electronic sensor devices Aug 15, 2022 Issued
Array ( [id] => 19936877 [patent_doc_number] => 12310098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Semiconductor structure having a semiconductor substrate and an isolation component [patent_app_type] => utility [patent_app_number] => 17/886200 [patent_app_country] => US [patent_app_date] => 2022-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 0 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17886200 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/886200
Semiconductor structure having a semiconductor substrate and an isolation component Aug 10, 2022 Issued
Array ( [id] => 18040213 [patent_doc_number] => 20220384430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => ELECTRODE STRUCTURE, SEMICONDUCTOR STRUCTURE, AND MANUFACTURING METHOD OF ELECTRODE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/886230 [patent_app_country] => US [patent_app_date] => 2022-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6338 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17886230 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/886230
ELECTRODE STRUCTURE, SEMICONDUCTOR STRUCTURE, AND MANUFACTURING METHOD OF ELECTRODE STRUCTURE Aug 10, 2022 Pending
Array ( [id] => 18040210 [patent_doc_number] => 20220384427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => DRIVING CHIP, SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/886161 [patent_app_country] => US [patent_app_date] => 2022-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5757 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17886161 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/886161
Semiconductor structure having a semiconductor substrate and an isolation component Aug 10, 2022 Issued
Array ( [id] => 20566142 [patent_doc_number] => 12568769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Memory device having a first layer disposed between a memory element and a switching element thereof [patent_app_type] => utility [patent_app_number] => 17/884790 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5746 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884790 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884790
Memory device having a first layer disposed between a memory element and a switching element thereof Aug 9, 2022 Issued
Array ( [id] => 18959024 [patent_doc_number] => 20240047351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => MULTISTEP ETCH FOR DIRECT CHIP ATTACH (DCA) SUBSTRATES, AND ASSOCIATED SYSTEMS AND DEVICES [patent_app_type] => utility [patent_app_number] => 17/882441 [patent_app_country] => US [patent_app_date] => 2022-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17882441 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/882441
MULTISTEP ETCH FOR DIRECT CHIP ATTACH (DCA) SUBSTRATES, AND ASSOCIATED SYSTEMS AND DEVICES Aug 4, 2022 Pending
Array ( [id] => 18272482 [patent_doc_number] => 20230093724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR WAFERS [patent_app_type] => utility [patent_app_number] => 17/876067 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8909 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876067 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/876067
MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR WAFERS Jul 27, 2022 Abandoned
Array ( [id] => 18789587 [patent_doc_number] => 20230378280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => PREPARATION METHOD OF DOUBLE-T-SHAPED GATE BASED ON DOUBLE-LAYER PASSIVATION ACCURATE ETCHING [patent_app_type] => utility [patent_app_number] => 18/030516 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18030516 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/030516
PREPARATION METHOD OF DOUBLE-T-SHAPED GATE BASED ON DOUBLE-LAYER PASSIVATION ACCURATE ETCHING Jul 27, 2022 Pending
Array ( [id] => 18008761 [patent_doc_number] => 20220367528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/876063 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4586 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876063 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/876063
Thin film transistor semiconductor device Jul 27, 2022 Issued
Array ( [id] => 17993668 [patent_doc_number] => 20220359705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING GATE OR CONTACT PLUGS [patent_app_type] => utility [patent_app_number] => 17/871693 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13070 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17871693 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/871693
Self-aligned gate endcap (SAGE) architecture having gate or contact plugs Jul 21, 2022 Issued
Array ( [id] => 18008699 [patent_doc_number] => 20220367466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => Semiconductor Devices with System on Chip Devices [patent_app_type] => utility [patent_app_number] => 17/870296 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870296 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/870296
Method of manufacturing semiconductor devices with system on chip devices Jul 20, 2022 Issued
Array ( [id] => 19679481 [patent_doc_number] => 12191354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Vertical transistors having at least 50% grain boundaries offset between top and bottom source/drain regions and the channel region that is vertically therebetween [patent_app_type] => utility [patent_app_number] => 17/860325 [patent_app_country] => US [patent_app_date] => 2022-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 8842 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17860325 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/860325
Vertical transistors having at least 50% grain boundaries offset between top and bottom source/drain regions and the channel region that is vertically therebetween Jul 7, 2022 Issued
Array ( [id] => 19467980 [patent_doc_number] => 20240321650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 18/579056 [patent_app_country] => US [patent_app_date] => 2022-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21267 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18579056 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/579056
SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS Jul 6, 2022 Pending
Array ( [id] => 18156126 [patent_doc_number] => 11569117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => 3D semiconductor device and structure with single-crystal layers [patent_app_type] => utility [patent_app_number] => 17/855775 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 90 [patent_figures_cnt] => 346 [patent_no_of_words] => 79590 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17855775 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/855775
3D semiconductor device and structure with single-crystal layers Jun 29, 2022 Issued
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