Search

John M Jillions

Examiner (ID: 5411)

Most Active Art Unit
2405
Art Unit(s)
2605, 2899, 3654, 2402, 2405, 3631, 3653, 3503
Total Applications
2304
Issued Applications
2137
Pending Applications
48
Abandoned Applications
119

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 350729 [patent_doc_number] => 07496731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-24 [patent_title] => 'Two dimensional addressing of a matrix-vector register array' [patent_app_type] => utility [patent_app_number] => 11/850920 [patent_app_country] => US [patent_app_date] => 2007-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7221 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/496/07496731.pdf [firstpage_image] =>[orig_patent_app_number] => 11850920 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/850920
Two dimensional addressing of a matrix-vector register array Sep 5, 2007 Issued
Array ( [id] => 5706632 [patent_doc_number] => 20060195680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'Computer instruction value field having an embedded sign' [patent_app_type] => utility [patent_app_number] => 11/406031 [patent_app_country] => US [patent_app_date] => 2006-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3028 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20060195680.pdf [firstpage_image] =>[orig_patent_app_number] => 11406031 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/406031
Computer instruction value field having an embedded sign Apr 17, 2006 Abandoned
Array ( [id] => 5867123 [patent_doc_number] => 20060101254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Start transactional execution (STE) instruction to support transactional program execution' [patent_app_type] => utility [patent_app_number] => 11/296599 [patent_app_country] => US [patent_app_date] => 2005-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5341 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20060101254.pdf [firstpage_image] =>[orig_patent_app_number] => 11296599 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/296599
Start transactional execution (STE) instruction to support transactional program execution Dec 5, 2005 Issued
Array ( [id] => 5058630 [patent_doc_number] => 20070061552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Architecture of program address generation capable of executing wait and delay instructions' [patent_app_type] => utility [patent_app_number] => 11/225112 [patent_app_country] => US [patent_app_date] => 2005-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3720 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20070061552.pdf [firstpage_image] =>[orig_patent_app_number] => 11225112 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/225112
Architecture of program address generation capable of executing wait and delay instructions Sep 13, 2005 Abandoned
Array ( [id] => 316884 [patent_doc_number] => 07526632 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-04-28 [patent_title] => 'System, apparatus and method for implementing multifunctional memory in reconfigurable data path processing' [patent_app_type] => utility [patent_app_number] => 10/971372 [patent_app_country] => US [patent_app_date] => 2004-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 8531 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/526/07526632.pdf [firstpage_image] =>[orig_patent_app_number] => 10971372 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/971372
System, apparatus and method for implementing multifunctional memory in reconfigurable data path processing Oct 21, 2004 Issued
Array ( [id] => 498078 [patent_doc_number] => 07216216 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-08 [patent_title] => 'Register window management using first pipeline to change current window and second pipeline to read operand from old window and write operand to new window' [patent_app_type] => utility [patent_app_number] => 10/881556 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12281 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/216/07216216.pdf [firstpage_image] =>[orig_patent_app_number] => 10881556 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/881556
Register window management using first pipeline to change current window and second pipeline to read operand from old window and write operand to new window Jun 29, 2004 Issued
Array ( [id] => 599974 [patent_doc_number] => 07441105 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-10-21 [patent_title] => 'Reducing multiplexer circuitry for operand select logic associated with a processor' [patent_app_type] => utility [patent_app_number] => 10/870749 [patent_app_country] => US [patent_app_date] => 2004-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6210 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/441/07441105.pdf [firstpage_image] =>[orig_patent_app_number] => 10870749 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/870749
Reducing multiplexer circuitry for operand select logic associated with a processor Jun 15, 2004 Issued
Array ( [id] => 5771024 [patent_doc_number] => 20060020945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-26 [patent_title] => 'System, circuitry and method for parallel processing real-time signal with open structure' [patent_app_type] => utility [patent_app_number] => 10/863655 [patent_app_country] => US [patent_app_date] => 2004-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4538 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20060020945.pdf [firstpage_image] =>[orig_patent_app_number] => 10863655 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/863655
System, circuitry and method for parallel processing real-time signal with open structure Jun 6, 2004 Abandoned
Array ( [id] => 7353063 [patent_doc_number] => 20040193859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-30 [patent_title] => 'Processor and compiler' [patent_app_type] => new [patent_app_number] => 10/805381 [patent_app_country] => US [patent_app_date] => 2004-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 61 [patent_figures_cnt] => 61 [patent_no_of_words] => 12505 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20040193859.pdf [firstpage_image] =>[orig_patent_app_number] => 10805381 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/805381
Processor and compiler for decoding an instruction and executing the decoded instruction with conditional execution flags Mar 21, 2004 Issued
Array ( [id] => 868800 [patent_doc_number] => 07370180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-06 [patent_title] => 'Bit field extraction with sign or zero extend' [patent_app_type] => utility [patent_app_number] => 10/793954 [patent_app_country] => US [patent_app_date] => 2004-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7525 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/370/07370180.pdf [firstpage_image] =>[orig_patent_app_number] => 10793954 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/793954
Bit field extraction with sign or zero extend Mar 7, 2004 Issued
Array ( [id] => 7277478 [patent_doc_number] => 20040236929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Logic circuit and program for executing thereon' [patent_app_type] => new [patent_app_number] => 10/790797 [patent_app_country] => US [patent_app_date] => 2004-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4723 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20040236929.pdf [firstpage_image] =>[orig_patent_app_number] => 10790797 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/790797
Logic circuit and program for executing thereon Mar 2, 2004 Abandoned
Array ( [id] => 7052469 [patent_doc_number] => 20050188188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'Methods and apparatus for early loop bottom detection in digital signal processors' [patent_app_type] => utility [patent_app_number] => 10/786968 [patent_app_country] => US [patent_app_date] => 2004-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3942 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20050188188.pdf [firstpage_image] =>[orig_patent_app_number] => 10786968 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/786968
Methods and apparatus for early loop bottom detection in digital signal processors Feb 24, 2004 Issued
Array ( [id] => 305625 [patent_doc_number] => 07536534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Processor capable of being switched among a plurality of operating modes, and method of designing said processor' [patent_app_type] => utility [patent_app_number] => 10/785671 [patent_app_country] => US [patent_app_date] => 2004-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 11029 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/536/07536534.pdf [firstpage_image] =>[orig_patent_app_number] => 10785671 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/785671
Processor capable of being switched among a plurality of operating modes, and method of designing said processor Feb 23, 2004 Issued
Array ( [id] => 7052467 [patent_doc_number] => 20050188186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'Obtaining execution path information in an instruction sampling system' [patent_app_type] => utility [patent_app_number] => 10/784730 [patent_app_country] => US [patent_app_date] => 2004-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3502 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20050188186.pdf [firstpage_image] =>[orig_patent_app_number] => 10784730 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/784730
Obtaining execution path information in an instruction sampling system Feb 22, 2004 Abandoned
Array ( [id] => 7474209 [patent_doc_number] => 20040168047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Processor and compiler for creating program for the processor' [patent_app_type] => new [patent_app_number] => 10/783282 [patent_app_country] => US [patent_app_date] => 2004-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7736 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20040168047.pdf [firstpage_image] =>[orig_patent_app_number] => 10783282 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/783282
Processor and compiler for creating program for the processor Feb 19, 2004 Abandoned
Array ( [id] => 7222756 [patent_doc_number] => 20050055539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Methods and apparatus for general deferred execution processors' [patent_app_type] => utility [patent_app_number] => 10/773673 [patent_app_country] => US [patent_app_date] => 2004-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 9962 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20050055539.pdf [firstpage_image] =>[orig_patent_app_number] => 10773673 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/773673
Methods and apparatus for storing expanded width instructions in a VLIW memory for deferred execution Feb 5, 2004 Issued
Array ( [id] => 465946 [patent_doc_number] => 07243219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-10 [patent_title] => 'Predicting instruction branches with a plurality of global predictors using varying amounts of history instruction' [patent_app_type] => utility [patent_app_number] => 10/743711 [patent_app_country] => US [patent_app_date] => 2003-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3605 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/243/07243219.pdf [firstpage_image] =>[orig_patent_app_number] => 10743711 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/743711
Predicting instruction branches with a plurality of global predictors using varying amounts of history instruction Dec 23, 2003 Issued
Array ( [id] => 427794 [patent_doc_number] => 07272700 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-18 [patent_title] => 'Methods and apparatus for indirect compound VLIW execution using operand address mapping techniques' [patent_app_type] => utility [patent_app_number] => 10/745267 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 31 [patent_no_of_words] => 13936 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/272/07272700.pdf [firstpage_image] =>[orig_patent_app_number] => 10745267 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/745267
Methods and apparatus for indirect compound VLIW execution using operand address mapping techniques Dec 22, 2003 Issued
Array ( [id] => 6999662 [patent_doc_number] => 20050138335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Methods and apparatus to control power consumption within a processor' [patent_app_type] => utility [patent_app_number] => 10/744719 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6049 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20050138335.pdf [firstpage_image] =>[orig_patent_app_number] => 10744719 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/744719
Methods and apparatus to control functional blocks within a processor Dec 22, 2003 Issued
10/746018 Architecture and method for reconfigurable data path processing Dec 22, 2003 Abandoned
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