Search

John M Jillions

Examiner (ID: 5411)

Most Active Art Unit
2405
Art Unit(s)
2605, 2899, 3654, 2402, 2405, 3631, 3653, 3503
Total Applications
2304
Issued Applications
2137
Pending Applications
48
Abandoned Applications
119

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7473993 [patent_doc_number] => 20040054874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Data processing device with a spare field in the instruction' [patent_app_type] => new [patent_app_number] => 10/612934 [patent_app_country] => US [patent_app_date] => 2003-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20040054874.pdf [firstpage_image] =>[orig_patent_app_number] => 10612934 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/612934
Data processing device with a spare field in the instruction Jul 6, 2003 Abandoned
Array ( [id] => 7084923 [patent_doc_number] => 20050050303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Hierarchical reorder buffers for controlling speculative execution in a multi-cluster system' [patent_app_type] => utility [patent_app_number] => 10/611380 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4605 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20050050303.pdf [firstpage_image] =>[orig_patent_app_number] => 10611380 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/611380
Hierarchical reorder buffers for controlling speculative execution in a multi-cluster system Jun 29, 2003 Abandoned
Array ( [id] => 7449162 [patent_doc_number] => 20040268093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Cross-thread register sharing technique' [patent_app_type] => new [patent_app_number] => 10/609264 [patent_app_country] => US [patent_app_date] => 2003-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1897 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20040268093.pdf [firstpage_image] =>[orig_patent_app_number] => 10609264 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/609264
Cross-thread register sharing technique Jun 25, 2003 Abandoned
Array ( [id] => 7174305 [patent_doc_number] => 20040078555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Processor having a finite field arithmetic unit' [patent_app_type] => new [patent_app_number] => 10/459907 [patent_app_country] => US [patent_app_date] => 2003-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9228 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20040078555.pdf [firstpage_image] =>[orig_patent_app_number] => 10459907 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/459907
Processor having a finite field arithmetic unit utilizing an array of multipliers and adders Jun 10, 2003 Issued
Array ( [id] => 7333247 [patent_doc_number] => 20040255105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Eliminating the overhead of setup and pipeline delays in deep-pipelined architectures' [patent_app_type] => new [patent_app_number] => 10/459016 [patent_app_country] => US [patent_app_date] => 2003-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8397 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20040255105.pdf [firstpage_image] =>[orig_patent_app_number] => 10459016 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/459016
Processor employing loadable configuration parameters to reduce or eliminate setup and pipeline delays in a pipeline system Jun 10, 2003 Issued
Array ( [id] => 860408 [patent_doc_number] => 07376819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-20 [patent_title] => 'Data processor with selectable word length' [patent_app_type] => utility [patent_app_number] => 10/457920 [patent_app_country] => US [patent_app_date] => 2003-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 36 [patent_no_of_words] => 21764 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/376/07376819.pdf [firstpage_image] =>[orig_patent_app_number] => 10457920 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/457920
Data processor with selectable word length Jun 10, 2003 Issued
Array ( [id] => 7333243 [patent_doc_number] => 20040255103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Method and system for terminating unnecessary processing of a conditional instruction in a processor' [patent_app_type] => new [patent_app_number] => 10/459283 [patent_app_country] => US [patent_app_date] => 2003-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2977 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20040255103.pdf [firstpage_image] =>[orig_patent_app_number] => 10459283 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/459283
Method and system for terminating unnecessary processing of a conditional instruction in a processor Jun 10, 2003 Abandoned
Array ( [id] => 7293449 [patent_doc_number] => 20040111592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Microprocessor performing pipeline processing of a plurality of stages' [patent_app_type] => new [patent_app_number] => 10/445831 [patent_app_country] => US [patent_app_date] => 2003-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7508 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20040111592.pdf [firstpage_image] =>[orig_patent_app_number] => 10445831 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/445831
Microprocessor performing pipeline processing of a plurality of stages May 27, 2003 Abandoned
Array ( [id] => 362563 [patent_doc_number] => 07487338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'Data processor for modifying and executing operation of instruction code according to the indication of other instruction code' [patent_app_type] => utility [patent_app_number] => 10/443768 [patent_app_country] => US [patent_app_date] => 2003-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 39 [patent_no_of_words] => 16489 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/487/07487338.pdf [firstpage_image] =>[orig_patent_app_number] => 10443768 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/443768
Data processor for modifying and executing operation of instruction code according to the indication of other instruction code May 22, 2003 Issued
Array ( [id] => 7277477 [patent_doc_number] => 20040236928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'System and method for improved branch performance in pipelined computer architectures' [patent_app_type] => new [patent_app_number] => 10/443673 [patent_app_country] => US [patent_app_date] => 2003-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5240 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20040236928.pdf [firstpage_image] =>[orig_patent_app_number] => 10443673 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/443673
System and method for improved branch performance in pipelined computer architectures May 21, 2003 Issued
Array ( [id] => 633370 [patent_doc_number] => 07134000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-07 [patent_title] => 'Methods and apparatus for instruction alignment including current instruction pointer logic responsive to instruction length information' [patent_app_type] => utility [patent_app_number] => 10/442329 [patent_app_country] => US [patent_app_date] => 2003-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 8713 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/134/07134000.pdf [firstpage_image] =>[orig_patent_app_number] => 10442329 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/442329
Methods and apparatus for instruction alignment including current instruction pointer logic responsive to instruction length information May 20, 2003 Issued
Array ( [id] => 294145 [patent_doc_number] => 07546445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-09 [patent_title] => 'Information processor having delayed branch function with storing delay slot information together with branch history information' [patent_app_type] => utility [patent_app_number] => 10/438986 [patent_app_country] => US [patent_app_date] => 2003-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4798 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/546/07546445.pdf [firstpage_image] =>[orig_patent_app_number] => 10438986 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/438986
Information processor having delayed branch function with storing delay slot information together with branch history information May 15, 2003 Issued
Array ( [id] => 374922 [patent_doc_number] => 07475230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Method and apparatus for performing register file checkpointing to support speculative execution within a processor' [patent_app_type] => utility [patent_app_number] => 10/439909 [patent_app_country] => US [patent_app_date] => 2003-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4303 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/475/07475230.pdf [firstpage_image] =>[orig_patent_app_number] => 10439909 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/439909
Method and apparatus for performing register file checkpointing to support speculative execution within a processor May 15, 2003 Issued
Array ( [id] => 7436501 [patent_doc_number] => 20040230781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Method and system for predicting the execution of conditional instructions in a processor' [patent_app_type] => new [patent_app_number] => 10/439941 [patent_app_country] => US [patent_app_date] => 2003-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2290 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20040230781.pdf [firstpage_image] =>[orig_patent_app_number] => 10439941 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/439941
Method and system for predicting the execution of conditional instructions in a processor May 15, 2003 Abandoned
Array ( [id] => 796795 [patent_doc_number] => 07430652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-30 [patent_title] => 'Devices for performing multiple independent hardware acceleration operations and methods for performing same' [patent_app_type] => utility [patent_app_number] => 10/403419 [patent_app_country] => US [patent_app_date] => 2003-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10329 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/430/07430652.pdf [firstpage_image] =>[orig_patent_app_number] => 10403419 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/403419
Devices for performing multiple independent hardware acceleration operations and methods for performing same Mar 27, 2003 Issued
Array ( [id] => 7057332 [patent_doc_number] => 20050278507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'Long displacement instruction formats' [patent_app_type] => utility [patent_app_number] => 10/403417 [patent_app_country] => US [patent_app_date] => 2003-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2493 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20050278507.pdf [firstpage_image] =>[orig_patent_app_number] => 10403417 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/403417
Computer instructions for having extended signed displacement fields for finding instruction operands Mar 27, 2003 Issued
Array ( [id] => 7352988 [patent_doc_number] => 20040193846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-30 [patent_title] => 'Method and apparatus for utilizing multiple opportunity ports in a processor pipeline' [patent_app_type] => new [patent_app_number] => 10/402781 [patent_app_country] => US [patent_app_date] => 2003-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4639 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20040193846.pdf [firstpage_image] =>[orig_patent_app_number] => 10402781 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/402781
Method and apparatus for utilizing multiple opportunity ports in a processor pipeline Mar 27, 2003 Abandoned
Array ( [id] => 7291022 [patent_doc_number] => 20040148490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Multiple register load using a Very Long Instruction Word' [patent_app_type] => new [patent_app_number] => 10/397966 [patent_app_country] => US [patent_app_date] => 2003-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1662 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20040148490.pdf [firstpage_image] =>[orig_patent_app_number] => 10397966 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/397966
Multiple register load using a Very Long Instruction Word Mar 25, 2003 Abandoned
Array ( [id] => 7353023 [patent_doc_number] => 20040193851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-30 [patent_title] => 'System and method for increasing program execution speed' [patent_app_type] => new [patent_app_number] => 10/396493 [patent_app_country] => US [patent_app_date] => 2003-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1507 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20040193851.pdf [firstpage_image] =>[orig_patent_app_number] => 10396493 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/396493
System and method for increasing program execution speed Mar 25, 2003 Abandoned
Array ( [id] => 856286 [patent_doc_number] => 07380106 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-27 [patent_title] => 'Method and system for transferring data between a register in a processor and a point-to-point communication link' [patent_app_type] => utility [patent_app_number] => 10/377855 [patent_app_country] => US [patent_app_date] => 2003-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4970 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/380/07380106.pdf [firstpage_image] =>[orig_patent_app_number] => 10377855 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/377855
Method and system for transferring data between a register in a processor and a point-to-point communication link Feb 27, 2003 Issued
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