Search

John M Jillions

Examiner (ID: 5411)

Most Active Art Unit
2405
Art Unit(s)
2605, 2899, 3654, 2402, 2405, 3631, 3653, 3503
Total Applications
2304
Issued Applications
2137
Pending Applications
48
Abandoned Applications
119

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 490300 [patent_doc_number] => 07222227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Control device for speculative instruction execution with a branch instruction insertion, and method for same' [patent_app_type] => utility [patent_app_number] => 10/370508 [patent_app_country] => US [patent_app_date] => 2003-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 12219 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/222/07222227.pdf [firstpage_image] =>[orig_patent_app_number] => 10370508 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/370508
Control device for speculative instruction execution with a branch instruction insertion, and method for same Feb 23, 2003 Issued
Array ( [id] => 559446 [patent_doc_number] => 07178008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'Register access scheduling method for multi-bank register file of a super-scalar parallel processor' [patent_app_type] => utility [patent_app_number] => 10/370172 [patent_app_country] => US [patent_app_date] => 2003-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5826 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 402 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/178/07178008.pdf [firstpage_image] =>[orig_patent_app_number] => 10370172 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/370172
Register access scheduling method for multi-bank register file of a super-scalar parallel processor Feb 17, 2003 Issued
Array ( [id] => 7440412 [patent_doc_number] => 20040162964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Processor capable of switching/reconstituting architecture' [patent_app_type] => new [patent_app_number] => 10/367097 [patent_app_country] => US [patent_app_date] => 2003-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 17090 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20040162964.pdf [firstpage_image] =>[orig_patent_app_number] => 10367097 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/367097
Data processor with changeable architecture Feb 13, 2003 Issued
Array ( [id] => 6822925 [patent_doc_number] => 20030221086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-27 [patent_title] => 'Configurable stream processor apparatus and methods' [patent_app_type] => new [patent_app_number] => 10/367512 [patent_app_country] => US [patent_app_date] => 2003-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4063 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20030221086.pdf [firstpage_image] =>[orig_patent_app_number] => 10367512 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/367512
Configurable stream processor apparatus and methods Feb 12, 2003 Abandoned
Array ( [id] => 7476982 [patent_doc_number] => 20040098562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Configurable processor architecture' [patent_app_type] => new [patent_app_number] => 10/358985 [patent_app_country] => US [patent_app_date] => 2003-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2873 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20040098562.pdf [firstpage_image] =>[orig_patent_app_number] => 10358985 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/358985
Configurable processor architecture Feb 4, 2003 Abandoned
Array ( [id] => 7291039 [patent_doc_number] => 20040148497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Method and apparatus for determining an early reifetch address of a mispredicted conditional branch instruction in an out of order multi-issue processor' [patent_app_type] => new [patent_app_number] => 10/351850 [patent_app_country] => US [patent_app_date] => 2003-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4935 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20040148497.pdf [firstpage_image] =>[orig_patent_app_number] => 10351850 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/351850
Method and apparatus for determining an early reifetch address of a mispredicted conditional branch instruction in an out of order multi-issue processor Jan 26, 2003 Abandoned
Array ( [id] => 7445481 [patent_doc_number] => 20040003217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Data processing device with branch prediction mechanism' [patent_app_type] => new [patent_app_number] => 10/349930 [patent_app_country] => US [patent_app_date] => 2003-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5056 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20040003217.pdf [firstpage_image] =>[orig_patent_app_number] => 10349930 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/349930
Data processing device with branch prediction mechanism Jan 23, 2003 Abandoned
Array ( [id] => 392849 [patent_doc_number] => 07302553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-27 [patent_title] => 'Apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue' [patent_app_type] => utility [patent_app_number] => 10/351556 [patent_app_country] => US [patent_app_date] => 2003-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 7544 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/302/07302553.pdf [firstpage_image] =>[orig_patent_app_number] => 10351556 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/351556
Apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue Jan 22, 2003 Issued
Array ( [id] => 757690 [patent_doc_number] => 07024537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Data speculation based on addressing patterns identifying dual-purpose register' [patent_app_type] => utility [patent_app_number] => 10/348144 [patent_app_country] => US [patent_app_date] => 2003-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 22324 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/024/07024537.pdf [firstpage_image] =>[orig_patent_app_number] => 10348144 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/348144
Data speculation based on addressing patterns identifying dual-purpose register Jan 20, 2003 Issued
Array ( [id] => 7328717 [patent_doc_number] => 20040139299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Operand forwarding in a superscalar processor' [patent_app_type] => new [patent_app_number] => 10/341900 [patent_app_country] => US [patent_app_date] => 2003-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2070 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20040139299.pdf [firstpage_image] =>[orig_patent_app_number] => 10341900 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/341900
Operand forwarding in a superscalar processor Jan 13, 2003 Abandoned
Array ( [id] => 666986 [patent_doc_number] => 07103755 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Apparatus and method for realizing effective parallel execution of instructions in an information processor' [patent_app_type] => utility [patent_app_number] => 10/339414 [patent_app_country] => US [patent_app_date] => 2003-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8104 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/103/07103755.pdf [firstpage_image] =>[orig_patent_app_number] => 10339414 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/339414
Apparatus and method for realizing effective parallel execution of instructions in an information processor Jan 9, 2003 Issued
Array ( [id] => 7328730 [patent_doc_number] => 20040139305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Hardware-enabled instruction tracing' [patent_app_type] => new [patent_app_number] => 10/339727 [patent_app_country] => US [patent_app_date] => 2003-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10671 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20040139305.pdf [firstpage_image] =>[orig_patent_app_number] => 10339727 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/339727
Hardware-enabled instruction tracing Jan 8, 2003 Abandoned
Array ( [id] => 645574 [patent_doc_number] => 07124284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Method and apparatus for processing a complex instruction for execution and retirement' [patent_app_type] => utility [patent_app_number] => 10/337056 [patent_app_country] => US [patent_app_date] => 2003-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3755 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/124/07124284.pdf [firstpage_image] =>[orig_patent_app_number] => 10337056 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/337056
Method and apparatus for processing a complex instruction for execution and retirement Jan 5, 2003 Issued
Array ( [id] => 7673632 [patent_doc_number] => 20040128486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'System and method for multi-type instruction set architecture' [patent_app_type] => new [patent_app_number] => 10/334114 [patent_app_country] => US [patent_app_date] => 2002-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3986 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20040128486.pdf [firstpage_image] =>[orig_patent_app_number] => 10334114 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/334114
System and method of converting data formats and communicating between execution units Dec 30, 2002 Issued
Array ( [id] => 302015 [patent_doc_number] => 07539846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'SIMD processor with a subroutine control unit' [patent_app_type] => utility [patent_app_number] => 10/232152 [patent_app_country] => US [patent_app_date] => 2002-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1352 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/539/07539846.pdf [firstpage_image] =>[orig_patent_app_number] => 10232152 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/232152
SIMD processor with a subroutine control unit Aug 29, 2002 Issued
Array ( [id] => 6560549 [patent_doc_number] => 20020138657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Data transfer circuit and data transfer method' [patent_app_type] => new [patent_app_number] => 10/104411 [patent_app_country] => US [patent_app_date] => 2002-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3910 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20020138657.pdf [firstpage_image] =>[orig_patent_app_number] => 10104411 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/104411
Data transfer circuit and data transfer method Mar 21, 2002 Abandoned
Array ( [id] => 362551 [patent_doc_number] => 07487330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'Method and apparatus for transferring control in a computer system with dynamic compilation capability' [patent_app_type] => utility [patent_app_number] => 09/847776 [patent_app_country] => US [patent_app_date] => 2001-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6502 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/487/07487330.pdf [firstpage_image] =>[orig_patent_app_number] => 09847776 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/847776
Method and apparatus for transferring control in a computer system with dynamic compilation capability May 1, 2001 Issued
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