Search

John M. Lindlof

Examiner (ID: 9223, Phone: (571)270-1024 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
489
Issued Applications
316
Pending Applications
30
Abandoned Applications
150

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11445143 [patent_doc_number] => 20170046164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'HIGH PERFORMANCE RECOVERY FROM MISSPECULATION OF LOAD LATENCY' [patent_app_type] => utility [patent_app_number] => 14/865150 [patent_app_country] => US [patent_app_date] => 2015-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10473 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14865150 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/865150
HIGH PERFORMANCE RECOVERY FROM MISSPECULATION OF LOAD LATENCY Sep 24, 2015 Abandoned
Array ( [id] => 11530947 [patent_doc_number] => 20170090925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'Instruction and Logic for Interrupt and Exception Handling' [patent_app_type] => utility [patent_app_number] => 14/865715 [patent_app_country] => US [patent_app_date] => 2015-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 27526 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14865715 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/865715
Instruction and logic for interrupt and exception handling Sep 24, 2015 Issued
Array ( [id] => 11531126 [patent_doc_number] => 20170091103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'Instruction and Logic for Indirect Accesses' [patent_app_type] => utility [patent_app_number] => 14/866146 [patent_app_country] => US [patent_app_date] => 2015-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 22526 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14866146 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/866146
Instruction and Logic for Indirect Accesses Sep 24, 2015 Abandoned
Array ( [id] => 15231561 [patent_doc_number] => 10503502 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Data element rearrangement, processors, methods, systems, and instructions [patent_app_type] => utility [patent_app_number] => 14/865696 [patent_app_country] => US [patent_app_date] => 2015-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 31 [patent_no_of_words] => 30672 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14865696 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/865696
Data element rearrangement, processors, methods, systems, and instructions Sep 24, 2015 Issued
Array ( [id] => 12393096 [patent_doc_number] => 09965280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-08 [patent_title] => Instruction and logic for processor trace information for control flow integrity [patent_app_type] => utility [patent_app_number] => 14/866254 [patent_app_country] => US [patent_app_date] => 2015-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 29 [patent_no_of_words] => 21889 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14866254 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/866254
Instruction and logic for processor trace information for control flow integrity Sep 24, 2015 Issued
Array ( [id] => 11365987 [patent_doc_number] => 20170003969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'VARIABLE LATENCY PIPE FOR INTERLEAVING INSTRUCTION TAGS IN A MICROPROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/755570 [patent_app_country] => US [patent_app_date] => 2015-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5552 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14755570 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/755570
Variable latency pipe for interleaving instruction tags in a microprocessor Jun 29, 2015 Issued
Array ( [id] => 10376716 [patent_doc_number] => 20150261723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'METHOD AND SYSTEM FOR MANAGING HARDWARE RESOURCES TO IMPLEMENT SYSTEM FUNCTIONS USING AN ADAPTIVE COMPUTING ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/714993 [patent_app_country] => US [patent_app_date] => 2015-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9671 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14714993 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/714993
Method and system for managing hardware resources to implement system functions using an adaptive computing architecture May 17, 2015 Issued
Array ( [id] => 12255932 [patent_doc_number] => 09928075 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-27 [patent_title] => 'Load queue entry reuse for operand store compare history table update' [patent_app_type] => utility [patent_app_number] => 14/621579 [patent_app_country] => US [patent_app_date] => 2015-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4660 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14621579 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/621579
Load queue entry reuse for operand store compare history table update Feb 12, 2015 Issued
Array ( [id] => 10210625 [patent_doc_number] => 20150095616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'DATA PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/565234 [patent_app_country] => US [patent_app_date] => 2014-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13176 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14565234 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/565234
DATA PROCESSOR Dec 8, 2014 Abandoned
Array ( [id] => 10258091 [patent_doc_number] => 20150143088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'VECTOR ELEMENT ROTATE AND INSERT UNDER MASK INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 14/561276 [patent_app_country] => US [patent_app_date] => 2014-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 18654 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14561276 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/561276
Vector element rotate and insert under mask instruction Dec 4, 2014 Issued
Array ( [id] => 9933815 [patent_doc_number] => 20150082007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'REGISTER MAPPING WITH MULTIPLE INSTRUCTION SETS' [patent_app_type] => utility [patent_app_number] => 14/548800 [patent_app_country] => US [patent_app_date] => 2014-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3367 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14548800 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/548800
REGISTER MAPPING WITH MULTIPLE INSTRUCTION SETS Nov 19, 2014 Abandoned
Array ( [id] => 9912074 [patent_doc_number] => 20150067277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'MULTIPROCESSOR SYSTEM FOR RESTRICTING AN ACCESS REQUEST TO A SHARED RESOURCE' [patent_app_type] => utility [patent_app_number] => 14/533870 [patent_app_country] => US [patent_app_date] => 2014-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5832 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14533870 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/533870
MULTIPROCESSOR SYSTEM FOR RESTRICTING AN ACCESS REQUEST TO A SHARED RESOURCE Nov 4, 2014 Abandoned
Array ( [id] => 10665727 [patent_doc_number] => 20160011870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'INSTRUCTION SET FOR ELIMINATING MISALIGNED MEMORY ACCESSES DURING PROCESSING OF AN ARRAY HAVING MISALIGNED DATA ROWS' [patent_app_type] => utility [patent_app_number] => 14/327534 [patent_app_country] => US [patent_app_date] => 2014-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 17054 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14327534 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/327534
Instruction set for eliminating misaligned memory accesses during processing of an array having misaligned data rows Jul 8, 2014 Issued
Array ( [id] => 12531993 [patent_doc_number] => 10007518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-26 [patent_title] => Register file structures combining vector and scalar data with global and local accesses [patent_app_type] => utility [patent_app_number] => 14/327066 [patent_app_country] => US [patent_app_date] => 2014-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5351 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14327066 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/327066
Register file structures combining vector and scalar data with global and local accesses Jul 8, 2014 Issued
Array ( [id] => 14426979 [patent_doc_number] => 10318293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Predication methods for vector processors [patent_app_type] => utility [patent_app_number] => 14/327038 [patent_app_country] => US [patent_app_date] => 2014-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5553 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 447 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14327038 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/327038
Predication methods for vector processors Jul 8, 2014 Issued
Array ( [id] => 15167247 [patent_doc_number] => 10489116 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-11-26 [patent_title] => Programmable integrated circuits with multiplexer and register pipelining circuitry [patent_app_type] => utility [patent_app_number] => 14/326828 [patent_app_country] => US [patent_app_date] => 2014-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6691 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14326828 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/326828
Programmable integrated circuits with multiplexer and register pipelining circuitry Jul 8, 2014 Issued
Array ( [id] => 10665730 [patent_doc_number] => 20160011875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'UNDEFINED INSTRUCTION RECODING' [patent_app_type] => utility [patent_app_number] => 14/325981 [patent_app_country] => US [patent_app_date] => 2014-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14325981 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/325981
UNDEFINED INSTRUCTION RECODING Jul 7, 2014 Abandoned
Array ( [id] => 9800780 [patent_doc_number] => 20150012723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-08 [patent_title] => 'PROCESSOR USING MINI-CORES' [patent_app_type] => utility [patent_app_number] => 14/324302 [patent_app_country] => US [patent_app_date] => 2014-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7891 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14324302 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/324302
PROCESSOR USING MINI-CORES Jul 6, 2014 Abandoned
Array ( [id] => 12114233 [patent_doc_number] => 09870226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-16 [patent_title] => 'Control of switching between executed mechanisms' [patent_app_type] => utility [patent_app_number] => 14/323040 [patent_app_country] => US [patent_app_date] => 2014-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4924 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14323040 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/323040
Control of switching between executed mechanisms Jul 2, 2014 Issued
Array ( [id] => 9866669 [patent_doc_number] => 20150046688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'METHOD OF GENERATING PROCESSOR TEST INSTRUCTION SEQUENCE AND GENERATING APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/322020 [patent_app_country] => US [patent_app_date] => 2014-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8885 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14322020 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/322020
METHOD OF GENERATING PROCESSOR TEST INSTRUCTION SEQUENCE AND GENERATING APPARATUS Jul 1, 2014 Abandoned
Menu