Search

John M. Lindlof

Examiner (ID: 10913, Phone: (571)270-1024 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
492
Issued Applications
319
Pending Applications
30
Abandoned Applications
150

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9800780 [patent_doc_number] => 20150012723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-08 [patent_title] => 'PROCESSOR USING MINI-CORES' [patent_app_type] => utility [patent_app_number] => 14/324302 [patent_app_country] => US [patent_app_date] => 2014-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7891 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14324302 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/324302
PROCESSOR USING MINI-CORES Jul 6, 2014 Abandoned
Array ( [id] => 12114233 [patent_doc_number] => 09870226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-16 [patent_title] => 'Control of switching between executed mechanisms' [patent_app_type] => utility [patent_app_number] => 14/323040 [patent_app_country] => US [patent_app_date] => 2014-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4924 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14323040 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/323040
Control of switching between executed mechanisms Jul 2, 2014 Issued
Array ( [id] => 9866669 [patent_doc_number] => 20150046688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'METHOD OF GENERATING PROCESSOR TEST INSTRUCTION SEQUENCE AND GENERATING APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/322020 [patent_app_country] => US [patent_app_date] => 2014-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8885 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14322020 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/322020
METHOD OF GENERATING PROCESSOR TEST INSTRUCTION SEQUENCE AND GENERATING APPARATUS Jul 1, 2014 Abandoned
Array ( [id] => 16698603 [patent_doc_number] => 10949200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Methods and apparatus for executing data-dependent threads in parallel [patent_app_type] => utility [patent_app_number] => 14/898894 [patent_app_country] => US [patent_app_date] => 2014-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 19553 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 554 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14898894 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/898894
Methods and apparatus for executing data-dependent threads in parallel Jun 12, 2014 Issued
Array ( [id] => 13017279 [patent_doc_number] => 10031754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Kick-started run-to-completion processor having no instruction counter [patent_app_type] => utility [patent_app_number] => 14/267298 [patent_app_country] => US [patent_app_date] => 2014-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7038 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14267298 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/267298
Kick-started run-to-completion processor having no instruction counter Apr 30, 2014 Issued
Array ( [id] => 13017281 [patent_doc_number] => 10031755 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Kick-started run-to-completion processing method that does not involve an instruction counter [patent_app_type] => utility [patent_app_number] => 14/267329 [patent_app_country] => US [patent_app_date] => 2014-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7038 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14267329 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/267329
Kick-started run-to-completion processing method that does not involve an instruction counter Apr 30, 2014 Issued
Array ( [id] => 11752256 [patent_doc_number] => 09710268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Reducing latency for pointer chasing loads' [patent_app_type] => utility [patent_app_number] => 14/264789 [patent_app_country] => US [patent_app_date] => 2014-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9395 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14264789 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/264789
Reducing latency for pointer chasing loads Apr 28, 2014 Issued
Array ( [id] => 10922171 [patent_doc_number] => 20140325191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'SEMICONDUCTOR TEST APPARATUS FOR CONTROLLING TESTER' [patent_app_type] => utility [patent_app_number] => 14/265068 [patent_app_country] => US [patent_app_date] => 2014-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5936 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14265068 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/265068
Semiconductor test apparatus for controlling tester Apr 28, 2014 Issued
Array ( [id] => 10424789 [patent_doc_number] => 20150309800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'Instruction That Performs A Scatter Write' [patent_app_type] => utility [patent_app_number] => 14/261097 [patent_app_country] => US [patent_app_date] => 2014-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8525 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14261097 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/261097
Instruction that performs a scatter write Apr 23, 2014 Issued
Array ( [id] => 10376529 [patent_doc_number] => 20150261537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'METHOD OF DECODING INSTRUCTIONS IN MICROPROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/259763 [patent_app_country] => US [patent_app_date] => 2014-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2825 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14259763 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/259763
METHOD OF DECODING INSTRUCTIONS IN MICROPROCESSOR Apr 22, 2014 Abandoned
Array ( [id] => 10401475 [patent_doc_number] => 20150286484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'PROCESSOR SUBROUTINE CACHE' [patent_app_type] => utility [patent_app_number] => 14/245667 [patent_app_country] => US [patent_app_date] => 2014-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4049 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14245667 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/245667
Processor subroutine cache Apr 3, 2014 Issued
Array ( [id] => 11875360 [patent_doc_number] => 09747132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-29 [patent_title] => 'Multi-core processor using former-stage pipeline portions and latter-stage pipeline portions assigned based on decode results in former-stage pipeline portions' [patent_app_type] => utility [patent_app_number] => 14/244994 [patent_app_country] => US [patent_app_date] => 2014-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3339 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 844 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14244994 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/244994
Multi-core processor using former-stage pipeline portions and latter-stage pipeline portions assigned based on decode results in former-stage pipeline portions Apr 3, 2014 Issued
Array ( [id] => 10392910 [patent_doc_number] => 20150277917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'HYBRID BIT-SLICED DICTIONARY ENCODING FOR FAST INDEX-BASED OPERATIONS' [patent_app_type] => utility [patent_app_number] => 14/242778 [patent_app_country] => US [patent_app_date] => 2014-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7372 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14242778 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/242778
Hybrid bit-sliced dictionary encoding for fast index-based operations Mar 31, 2014 Issued
Array ( [id] => 10439191 [patent_doc_number] => 20150324203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'HAZARD PREDICTION FOR A GROUP OF MEMORY ACCESS INSTRUCTIONS USING A BUFFER ASSOCIATED WITH BRANCH PREDICTION' [patent_app_type] => utility [patent_app_number] => 14/203896 [patent_app_country] => US [patent_app_date] => 2014-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13575 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14203896 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/203896
Hazard prediction for a group of memory access instructions using a buffer associated with branch prediction Mar 10, 2014 Issued
Array ( [id] => 11924540 [patent_doc_number] => 09792123 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'Indirect branch prediction' [patent_app_type] => utility [patent_app_number] => 14/169771 [patent_app_country] => US [patent_app_date] => 2014-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11070 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14169771 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/169771
Indirect branch prediction Jan 30, 2014 Issued
Array ( [id] => 9424450 [patent_doc_number] => 20140109101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-17 [patent_title] => 'EFFECTIVE SCHEDULING OF PRODUCER-CONSUMER PROCESSES IN A MULTI-PROCESSOR SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/141089 [patent_app_country] => US [patent_app_date] => 2013-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8306 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14141089 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/141089
Effective scheduling of producer-consumer processes in a multi-processor system Dec 25, 2013 Issued
Array ( [id] => 9992614 [patent_doc_number] => 09037834 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-19 [patent_title] => 'Method and system for managing hardware resources to implement system functions using an adaptive computing architecture' [patent_app_type] => utility [patent_app_number] => 14/082691 [patent_app_country] => US [patent_app_date] => 2013-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 9632 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14082691 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/082691
Method and system for managing hardware resources to implement system functions using an adaptive computing architecture Nov 17, 2013 Issued
Array ( [id] => 11786545 [patent_doc_number] => 09395980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-19 [patent_title] => 'Residual addition for video software techniques' [patent_app_type] => utility [patent_app_number] => 14/052225 [patent_app_country] => US [patent_app_date] => 2013-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4273 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14052225 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/052225
Residual addition for video software techniques Oct 10, 2013 Issued
Array ( [id] => 9265068 [patent_doc_number] => 20130346997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-26 [patent_title] => 'MECHANISM OF SUPPORTING SUB-COMMUNICATOR COLLECTIVES WITH O(64) COUNTERS AS OPPOSED TO ONE COUNTER FOR EACH SUB-COMMUNICATOR' [patent_app_type] => utility [patent_app_number] => 14/015098 [patent_app_country] => US [patent_app_date] => 2013-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4708 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14015098 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/015098
Mechanism of supporting sub-communicator collectives with o(64) counters as opposed to one counter for each sub-communicator Aug 29, 2013 Issued
Array ( [id] => 10786175 [patent_doc_number] => 20160132332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'SIGNAL PROCESSING DEVICE AND METHOD OF PERFORMING A BIT-EXPAND OPERATION' [patent_app_type] => utility [patent_app_number] => 14/898353 [patent_app_country] => US [patent_app_date] => 2013-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5219 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14898353 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/898353
SIGNAL PROCESSING DEVICE AND METHOD OF PERFORMING A BIT-EXPAND OPERATION Jun 17, 2013 Abandoned
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