
John M. Lindlof
Examiner (ID: 10913, Phone: (571)270-1024 , Office: P/2183 )
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2183 |
| Total Applications | 492 |
| Issued Applications | 319 |
| Pending Applications | 30 |
| Abandoned Applications | 150 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 309488
[patent_doc_number] => 07533251
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[patent_kind] => B2
[patent_issue_date] => 2009-05-12
[patent_title] => 'Semiconductor integrated circuit, development support system and execution history tracing method'
[patent_app_type] => utility
[patent_app_number] => 11/018965
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Array
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[patent_title] => 'Hardware stack having entries with a data portion and associated counter'
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Array
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[patent_title] => 'Method and apparatus for vector execution on a scalar machine'
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Array
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[patent_title] => 'Branch target aware instruction prefetching technique'
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Array
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Array
(
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Array
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[patent_title] => 'Very long instruction word (VLIW) computer having an efficient instruction code format'
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Array
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[id] => 5809363
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[patent_title] => 'Microcontroller having partial-twin structure'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/943834 | Microcontroller having partial-twin structure | Sep 16, 2004 | Abandoned |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/932730 | Pipelined processing | Sep 1, 2004 | Issued |
Array
(
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[patent_title] => 'Data processing apparatus and method for performing arithmetic operations in SIMD data processing'
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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