Search

John M. Lindlof

Examiner (ID: 10913, Phone: (571)270-1024 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
492
Issued Applications
319
Pending Applications
30
Abandoned Applications
150

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 309488 [patent_doc_number] => 07533251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'Semiconductor integrated circuit, development support system and execution history tracing method' [patent_app_type] => utility [patent_app_number] => 11/018965 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 52 [patent_no_of_words] => 19128 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/533/07533251.pdf [firstpage_image] =>[orig_patent_app_number] => 11018965 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/018965
Semiconductor integrated circuit, development support system and execution history tracing method Dec 21, 2004 Issued
Array ( [id] => 5695777 [patent_doc_number] => 20060155924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Hardware stack having entries with a data portion and associated counter' [patent_app_type] => utility [patent_app_number] => 11/012688 [patent_app_country] => US [patent_app_date] => 2004-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 6330 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20060155924.pdf [firstpage_image] =>[orig_patent_app_number] => 11012688 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/012688
Hardware stack having entries with a data portion and associated counter Dec 14, 2004 Issued
Array ( [id] => 5633470 [patent_doc_number] => 20060149941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Method and apparatus for vector execution on a scalar machine' [patent_app_type] => utility [patent_app_number] => 11/013122 [patent_app_country] => US [patent_app_date] => 2004-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10957 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20060149941.pdf [firstpage_image] =>[orig_patent_app_number] => 11013122 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/013122
Method and apparatus for vector execution on a scalar machine Dec 14, 2004 Issued
Array ( [id] => 188580 [patent_doc_number] => 07647477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-12 [patent_title] => 'Branch target aware instruction prefetching technique' [patent_app_type] => utility [patent_app_number] => 10/996027 [patent_app_country] => US [patent_app_date] => 2004-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3855 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/647/07647477.pdf [firstpage_image] =>[orig_patent_app_number] => 10996027 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/996027
Branch target aware instruction prefetching technique Nov 22, 2004 Issued
Array ( [id] => 7149383 [patent_doc_number] => 20050120348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Method of determining information about the processes which run in a program-controlled unit during the execution of a program by the program-controlled unit' [patent_app_type] => utility [patent_app_number] => 10/989880 [patent_app_country] => US [patent_app_date] => 2004-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 13167 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20050120348.pdf [firstpage_image] =>[orig_patent_app_number] => 10989880 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/989880
Method of determining information about the processes which run in a program-controlled unit during the execution of a program by the program-controlled unit Nov 15, 2004 Abandoned
Array ( [id] => 5809540 [patent_doc_number] => 20060095896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Apparatus, system, and method of removing exception related dependencies' [patent_app_type] => utility [patent_app_number] => 10/950675 [patent_app_country] => US [patent_app_date] => 2004-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4710 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095896.pdf [firstpage_image] =>[orig_patent_app_number] => 10950675 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/950675
Apparatus, system, and method of removing exception related dependencies Sep 27, 2004 Abandoned
Array ( [id] => 852095 [patent_doc_number] => 07383422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-03 [patent_title] => 'Very long instruction word (VLIW) computer having an efficient instruction code format' [patent_app_type] => utility [patent_app_number] => 10/949230 [patent_app_country] => US [patent_app_date] => 2004-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 8699 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/383/07383422.pdf [firstpage_image] =>[orig_patent_app_number] => 10949230 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/949230
Very long instruction word (VLIW) computer having an efficient instruction code format Sep 26, 2004 Issued
Array ( [id] => 5809363 [patent_doc_number] => 20060095719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Microcontroller having partial-twin structure' [patent_app_type] => utility [patent_app_number] => 10/943834 [patent_app_country] => US [patent_app_date] => 2004-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3059 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095719.pdf [firstpage_image] =>[orig_patent_app_number] => 10943834 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/943834
Microcontroller having partial-twin structure Sep 16, 2004 Abandoned
Array ( [id] => 8001149 [patent_doc_number] => 08082422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-20 [patent_title] => 'Pipelined processing' [patent_app_type] => utility [patent_app_number] => 10/932730 [patent_app_country] => US [patent_app_date] => 2004-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4552 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/082/08082422.pdf [firstpage_image] =>[orig_patent_app_number] => 10932730 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/932730
Pipelined processing Sep 1, 2004 Issued
Array ( [id] => 7184771 [patent_doc_number] => 20050125476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Data processing apparatus and method for performing arithmetic operations in SIMD data processing' [patent_app_type] => utility [patent_app_number] => 10/889362 [patent_app_country] => US [patent_app_date] => 2004-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 51 [patent_no_of_words] => 28362 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20050125476.pdf [firstpage_image] =>[orig_patent_app_number] => 10889362 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/889362
Data processing apparatus and method for performing arithmetic operations in SIMD data processing Jul 12, 2004 Issued
Array ( [id] => 7006793 [patent_doc_number] => 20050172106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Aliasing data processing registers' [patent_app_type] => utility [patent_app_number] => 10/889314 [patent_app_country] => US [patent_app_date] => 2004-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 51 [patent_no_of_words] => 28764 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20050172106.pdf [firstpage_image] =>[orig_patent_app_number] => 10889314 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/889314
Aliasing data processing registers Jul 12, 2004 Issued
Array ( [id] => 146583 [patent_doc_number] => 07689811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'Method and apparatus for constant generation in SIMD processing' [patent_app_type] => utility [patent_app_number] => 10/889364 [patent_app_country] => US [patent_app_date] => 2004-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 105 [patent_no_of_words] => 28625 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/689/07689811.pdf [firstpage_image] =>[orig_patent_app_number] => 10889364 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/889364
Method and apparatus for constant generation in SIMD processing Jul 12, 2004 Issued
Array ( [id] => 600331 [patent_doc_number] => 07437541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-14 [patent_title] => 'Atomically updating 64 bit fields in the 32 bit AIX kernel' [patent_app_type] => utility [patent_app_number] => 10/887439 [patent_app_country] => US [patent_app_date] => 2004-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4704 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/437/07437541.pdf [firstpage_image] =>[orig_patent_app_number] => 10887439 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/887439
Atomically updating 64 bit fields in the 32 bit AIX kernel Jul 7, 2004 Issued
Array ( [id] => 163317 [patent_doc_number] => 07676655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-09 [patent_title] => 'Single bit control of threads in a multithreaded multicore processor' [patent_app_type] => utility [patent_app_number] => 10/880917 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9217 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/676/07676655.pdf [firstpage_image] =>[orig_patent_app_number] => 10880917 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/880917
Single bit control of threads in a multithreaded multicore processor Jun 29, 2004 Issued
Array ( [id] => 7718468 [patent_doc_number] => 08095778 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-01-10 [patent_title] => 'Method and system for sharing functional units of a multithreaded processor' [patent_app_type] => utility [patent_app_number] => 10/880712 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9115 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/095/08095778.pdf [firstpage_image] =>[orig_patent_app_number] => 10880712 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/880712
Method and system for sharing functional units of a multithreaded processor Jun 29, 2004 Issued
Array ( [id] => 600328 [patent_doc_number] => 07437538 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-10-14 [patent_title] => 'Apparatus and method for reducing execution latency of floating point operations having special case operands' [patent_app_type] => utility [patent_app_number] => 10/881763 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9392 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/437/07437538.pdf [firstpage_image] =>[orig_patent_app_number] => 10881763 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/881763
Apparatus and method for reducing execution latency of floating point operations having special case operands Jun 29, 2004 Issued
Array ( [id] => 136357 [patent_doc_number] => 07702887 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-04-20 [patent_title] => 'Performance instrumentation in a fine grain multithreaded multicore processor' [patent_app_type] => utility [patent_app_number] => 10/881032 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13113 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/702/07702887.pdf [firstpage_image] =>[orig_patent_app_number] => 10881032 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/881032
Performance instrumentation in a fine grain multithreaded multicore processor Jun 29, 2004 Issued
Array ( [id] => 6979611 [patent_doc_number] => 20050289329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Conditional instruction for a single instruction, multiple data execution engine' [patent_app_type] => utility [patent_app_number] => 10/879460 [patent_app_country] => US [patent_app_date] => 2004-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3390 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20050289329.pdf [firstpage_image] =>[orig_patent_app_number] => 10879460 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/879460
Conditional instruction for a single instruction, multiple data execution engine Jun 28, 2004 Abandoned
Array ( [id] => 27305 [patent_doc_number] => 07802076 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'Method and apparatus to vectorize multiple input instructions' [patent_app_type] => utility [patent_app_number] => 10/874744 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3823 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/802/07802076.pdf [firstpage_image] =>[orig_patent_app_number] => 10874744 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/874744
Method and apparatus to vectorize multiple input instructions Jun 23, 2004 Issued
Array ( [id] => 6932558 [patent_doc_number] => 20050283593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-22 [patent_title] => 'Loop end prediction' [patent_app_type] => utility [patent_app_number] => 10/870548 [patent_app_country] => US [patent_app_date] => 2004-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4109 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20050283593.pdf [firstpage_image] =>[orig_patent_app_number] => 10870548 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/870548
Loop end prediction Jun 17, 2004 Abandoned
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