Search

John M. Lindlof

Examiner (ID: 9223, Phone: (571)270-1024 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
489
Issued Applications
316
Pending Applications
30
Abandoned Applications
150

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15530609 [patent_doc_number] => 20200057610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-20 [patent_title] => PROGRAMMABLE INTEGRATED CIRCUITS WITH MULTIPLEXER AND REGISTER PIPELINING CIRCUITRY [patent_app_type] => utility [patent_app_number] => 16/666066 [patent_app_country] => US [patent_app_date] => 2019-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6701 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16666066 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/666066
PROGRAMMABLE INTEGRATED CIRCUITS WITH MULTIPLEXER AND REGISTER PIPELINING CIRCUITRY Oct 27, 2019 Abandoned
Array ( [id] => 18119181 [patent_doc_number] => 11550574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Generating a vector predicate summary [patent_app_type] => utility [patent_app_number] => 17/273919 [patent_app_country] => US [patent_app_date] => 2019-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 7039 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17273919 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/273919
Generating a vector predicate summary Oct 16, 2019 Issued
Array ( [id] => 15653925 [patent_doc_number] => 20200089493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => MICROPROCESSOR INCLUDING AN EFFICIENCY LOGIC UNIT [patent_app_type] => utility [patent_app_number] => 16/654857 [patent_app_country] => US [patent_app_date] => 2019-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5696 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16654857 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/654857
Microprocessor including an efficiency logic unit Oct 15, 2019 Issued
Array ( [id] => 16745089 [patent_doc_number] => 10970079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Parallel dispatching of multi-operation instructions in a multi-slice computer processor [patent_app_type] => utility [patent_app_number] => 16/597488 [patent_app_country] => US [patent_app_date] => 2019-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7760 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16597488 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/597488
Parallel dispatching of multi-operation instructions in a multi-slice computer processor Oct 8, 2019 Issued
Array ( [id] => 17076655 [patent_doc_number] => 11113053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Data element comparison processors, methods, systems, and instructions [patent_app_type] => utility [patent_app_number] => 16/579394 [patent_app_country] => US [patent_app_date] => 2019-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 31 [patent_no_of_words] => 26274 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16579394 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/579394
Data element comparison processors, methods, systems, and instructions Sep 22, 2019 Issued
Array ( [id] => 19078591 [patent_doc_number] => 11947959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Re-using processing elements of an artificial intelligence processor [patent_app_type] => utility [patent_app_number] => 16/566370 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5929 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 392 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566370 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/566370
Re-using processing elements of an artificial intelligence processor Sep 9, 2019 Issued
Array ( [id] => 17269149 [patent_doc_number] => 11194574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-07 [patent_title] => Merging memory ordering tracking information for issued load instructions [patent_app_type] => utility [patent_app_number] => 16/521663 [patent_app_country] => US [patent_app_date] => 2019-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 13775 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16521663 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/521663
Merging memory ordering tracking information for issued load instructions Jul 24, 2019 Issued
Array ( [id] => 17744311 [patent_doc_number] => 11392378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Executing a set of load operations for a gather-load instruction and controlling handling of another instruction that depends on completion of the gather-load instruction [patent_app_type] => utility [patent_app_number] => 16/521748 [patent_app_country] => US [patent_app_date] => 2019-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7805 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16521748 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/521748
Executing a set of load operations for a gather-load instruction and controlling handling of another instruction that depends on completion of the gather-load instruction Jul 24, 2019 Issued
Array ( [id] => 17352180 [patent_doc_number] => 11226817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-18 [patent_title] => Prefetching workloads with dependent pointers [patent_app_type] => utility [patent_app_number] => 16/508671 [patent_app_country] => US [patent_app_date] => 2019-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 9419 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16508671 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/508671
Prefetching workloads with dependent pointers Jul 10, 2019 Issued
Array ( [id] => 16543296 [patent_doc_number] => 20200409711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => PROCESSOR INSTRUCTION SUPPORT FOR MITIGATING CONTROLLED-CHANNEL AND CACHE-BASED SIDE-CHANNEL ATTACKS [patent_app_type] => utility [patent_app_number] => 16/458015 [patent_app_country] => US [patent_app_date] => 2019-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30406 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16458015 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/458015
PROCESSOR INSTRUCTION SUPPORT FOR MITIGATING CONTROLLED-CHANNEL AND CACHE-BASED SIDE-CHANNEL ATTACKS Jun 28, 2019 Abandoned
Array ( [id] => 20203011 [patent_doc_number] => 12405790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Compute unit sorting for reduced divergence [patent_app_type] => utility [patent_app_number] => 16/457873 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3450 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16457873 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/457873
Compute unit sorting for reduced divergence Jun 27, 2019 Issued
Array ( [id] => 15042757 [patent_doc_number] => 20190332383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => EFFECTIVENESS AND PRIORITIZATION OF PREFETCHES [patent_app_type] => utility [patent_app_number] => 16/444598 [patent_app_country] => US [patent_app_date] => 2019-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16444598 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/444598
Effectiveness and prioritization of prefetches Jun 17, 2019 Issued
Array ( [id] => 16818626 [patent_doc_number] => 11003452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Effectiveness and prioritization of prefetches [patent_app_type] => utility [patent_app_number] => 16/444694 [patent_app_country] => US [patent_app_date] => 2019-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13013 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16444694 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/444694
Effectiveness and prioritization of prefetches Jun 17, 2019 Issued
Array ( [id] => 16423734 [patent_doc_number] => 20200348932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => MEMORY CONTROL SYSTEM WITH A SEQUENCE PROCESSING UNIT [patent_app_type] => utility [patent_app_number] => 16/441021 [patent_app_country] => US [patent_app_date] => 2019-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441021 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/441021
MEMORY CONTROL SYSTEM WITH A SEQUENCE PROCESSING UNIT Jun 13, 2019 Abandoned
Array ( [id] => 17031434 [patent_doc_number] => 11093245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Computer system and memory access technology [patent_app_type] => utility [patent_app_number] => 16/439335 [patent_app_country] => US [patent_app_date] => 2019-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 11996 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16439335 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/439335
Computer system and memory access technology Jun 11, 2019 Issued
Array ( [id] => 14901611 [patent_doc_number] => 20190294571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING DATAPATH STEERING [patent_app_type] => utility [patent_app_number] => 16/437328 [patent_app_country] => US [patent_app_date] => 2019-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7154 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16437328 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/437328
OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING DATAPATH STEERING Jun 10, 2019 Abandoned
Array ( [id] => 16844686 [patent_doc_number] => 11016771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Processor and instruction operation method [patent_app_type] => utility [patent_app_number] => 16/419121 [patent_app_country] => US [patent_app_date] => 2019-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7516 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16419121 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/419121
Processor and instruction operation method May 21, 2019 Issued
Array ( [id] => 16095331 [patent_doc_number] => 20200201652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => HANDLING EXCEPTIONS IN A MULTI-TILE PROCESSING ARRANGEMENT [patent_app_type] => utility [patent_app_number] => 16/419373 [patent_app_country] => US [patent_app_date] => 2019-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16419373 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/419373
Handling exceptions in a multi-tile processing arrangement May 21, 2019 Issued
Array ( [id] => 17877325 [patent_doc_number] => 11449338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Handling exceptions in a multi-tile processing arrangement [patent_app_type] => utility [patent_app_number] => 16/395386 [patent_app_country] => US [patent_app_date] => 2019-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 14100 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16395386 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/395386
Handling exceptions in a multi-tile processing arrangement Apr 25, 2019 Issued
Array ( [id] => 16972295 [patent_doc_number] => 11068267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => High bandwidth logical register flush recovery [patent_app_type] => utility [patent_app_number] => 16/392722 [patent_app_country] => US [patent_app_date] => 2019-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4741 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16392722 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/392722
High bandwidth logical register flush recovery Apr 23, 2019 Issued
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