Search

John M. Lindlof

Examiner (ID: 10913, Phone: (571)270-1024 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
492
Issued Applications
319
Pending Applications
30
Abandoned Applications
150

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15638501 [patent_doc_number] => 10592244 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Branch type logging in last branch registers [patent_app_type] => utility [patent_app_number] => 15/423143 [patent_app_country] => US [patent_app_date] => 2017-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13035 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15423143 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/423143
Branch type logging in last branch registers Feb 1, 2017 Issued
Array ( [id] => 13332601 [patent_doc_number] => 20180217838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => ULTRA LEAN VECTOR PROCESSOR [patent_app_type] => utility [patent_app_number] => 15/422014 [patent_app_country] => US [patent_app_date] => 2017-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15422014 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/422014
ULTRA LEAN VECTOR PROCESSOR Jan 31, 2017 Abandoned
Array ( [id] => 16864502 [patent_doc_number] => 11023242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Method and apparatus for asynchronous scheduling [patent_app_type] => utility [patent_app_number] => 15/417555 [patent_app_country] => US [patent_app_date] => 2017-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5596 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15417555 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/417555
Method and apparatus for asynchronous scheduling Jan 26, 2017 Issued
Array ( [id] => 13318393 [patent_doc_number] => 20180210734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => METHODS AND APPARATUS FOR PROCESSING SELF-MODIFYING CODES [patent_app_type] => utility [patent_app_number] => 15/417079 [patent_app_country] => US [patent_app_date] => 2017-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6154 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15417079 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/417079
METHODS AND APPARATUS FOR PROCESSING SELF-MODIFYING CODES Jan 25, 2017 Abandoned
Array ( [id] => 11651450 [patent_doc_number] => 20170147351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'VLIW INTERFACE DEVICE AND METHOD FOR CONTROLLING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/360271 [patent_app_country] => US [patent_app_date] => 2016-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15360271 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/360271
VLIW interface device and method for controlling the same Nov 22, 2016 Issued
Array ( [id] => 11494354 [patent_doc_number] => 20170068540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'HARDWARE ACCELERATED CONVERSION SYSTEM USING PATTERN MATCHING' [patent_app_type] => utility [patent_app_number] => 15/353472 [patent_app_country] => US [patent_app_date] => 2016-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11493 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15353472 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/353472
Hardware accelerated conversion system using pattern matching Nov 15, 2016 Issued
Array ( [id] => 11591580 [patent_doc_number] => 20170115991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'UNIFIED SHADOW REGISTER FILE AND PIPELINE ARCHITECTURE SUPPORTING SPECULATIVE ARCHITECTURAL STATES' [patent_app_type] => utility [patent_app_number] => 15/353507 [patent_app_country] => US [patent_app_date] => 2016-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11493 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15353507 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/353507
UNIFIED SHADOW REGISTER FILE AND PIPELINE ARCHITECTURE SUPPORTING SPECULATIVE ARCHITECTURAL STATES Nov 15, 2016 Abandoned
Array ( [id] => 11868290 [patent_doc_number] => 20170235575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'UNIFIED REGISTER FILE FOR SUPPORTING SPECULATIVE ARCHITECTURAL STATES' [patent_app_type] => utility [patent_app_number] => 15/353549 [patent_app_country] => US [patent_app_date] => 2016-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11494 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15353549 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/353549
Unified register file for supporting speculative architectural states Nov 15, 2016 Issued
Array ( [id] => 15313069 [patent_doc_number] => 10521239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Microprocessor accelerated code optimizer [patent_app_type] => utility [patent_app_number] => 15/283836 [patent_app_country] => US [patent_app_date] => 2016-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9206 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15283836 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/283836
Microprocessor accelerated code optimizer Oct 2, 2016 Issued
Array ( [id] => 13483071 [patent_doc_number] => 20180293078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => HANDLING EXCEPTIONAL CONDITIONS FOR VECTOR ARITHMETIC INSTRUCTION [patent_app_type] => utility [patent_app_number] => 15/769558 [patent_app_country] => US [patent_app_date] => 2016-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15769558 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/769558
Handling exceptional conditions for vector arithmetic instruction Sep 13, 2016 Issued
Array ( [id] => 11338486 [patent_doc_number] => 20160364242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-15 [patent_title] => 'LOAD QUEUE ENTRY REUSE FOR OPERAND STORE COMPARE HISTORY TABLE UPDATE' [patent_app_type] => utility [patent_app_number] => 15/252325 [patent_app_country] => US [patent_app_date] => 2016-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4716 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15252325 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/252325
Load queue entry reuse for operand store compare history table update Aug 30, 2016 Issued
Array ( [id] => 13948447 [patent_doc_number] => 10209998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => Multi-threading processor and a scheduling method thereof [patent_app_type] => utility [patent_app_number] => 15/229529 [patent_app_country] => US [patent_app_date] => 2016-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4226 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15229529 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/229529
Multi-threading processor and a scheduling method thereof Aug 4, 2016 Issued
Array ( [id] => 13068899 [patent_doc_number] => 10055229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-21 [patent_title] => Controlling processing of instructions in a processing pipeline [patent_app_type] => utility [patent_app_number] => 15/224802 [patent_app_country] => US [patent_app_date] => 2016-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9930 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15224802 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/224802
Controlling processing of instructions in a processing pipeline Jul 31, 2016 Issued
Array ( [id] => 11823827 [patent_doc_number] => 20170212764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'CONTROLLING PROCESSING OF INSTRUCTIONS IN A PROCESSING PIPELINE' [patent_app_type] => utility [patent_app_number] => 15/224810 [patent_app_country] => US [patent_app_date] => 2016-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9807 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15224810 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/224810
Controlling processing of instructions in a processing pipeline Jul 31, 2016 Issued
Array ( [id] => 17877328 [patent_doc_number] => 11449342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Hybrid block-based processor and custom function blocks [patent_app_type] => utility [patent_app_number] => 15/224624 [patent_app_country] => US [patent_app_date] => 2016-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 19269 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15224624 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/224624
Hybrid block-based processor and custom function blocks Jul 30, 2016 Issued
Array ( [id] => 13721411 [patent_doc_number] => 20170371660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => LOAD-STORE QUEUE FOR MULTIPLE PROCESSOR CORES [patent_app_type] => utility [patent_app_number] => 15/224591 [patent_app_country] => US [patent_app_date] => 2016-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34743 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15224591 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/224591
LOAD-STORE QUEUE FOR MULTIPLE PROCESSOR CORES Jul 30, 2016 Abandoned
Array ( [id] => 13721409 [patent_doc_number] => 20170371659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => LOAD-STORE QUEUE FOR BLOCK-BASED PROCESSOR [patent_app_type] => utility [patent_app_number] => 15/224587 [patent_app_country] => US [patent_app_date] => 2016-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29971 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15224587 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/224587
LOAD-STORE QUEUE FOR BLOCK-BASED PROCESSOR Jul 30, 2016 Abandoned
Array ( [id] => 12161069 [patent_doc_number] => 20180032335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'TRANSACTIONAL REGISTER FILE FOR A PROCESSOR' [patent_app_type] => utility [patent_app_number] => 15/224593 [patent_app_country] => US [patent_app_date] => 2016-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 31665 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15224593 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/224593
TRANSACTIONAL REGISTER FILE FOR A PROCESSOR Jul 30, 2016 Abandoned
Array ( [id] => 12161078 [patent_doc_number] => 20180032344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'OUT-OF-ORDER BLOCK-BASED PROCESSOR' [patent_app_type] => utility [patent_app_number] => 15/224592 [patent_app_country] => US [patent_app_date] => 2016-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 26334 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15224592 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/224592
OUT-OF-ORDER BLOCK-BASED PROCESSOR Jul 30, 2016 Abandoned
Array ( [id] => 12025713 [patent_doc_number] => 20170315812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'PARALLEL INSTRUCTION SCHEDULER FOR BLOCK ISA PROCESSOR' [patent_app_type] => utility [patent_app_number] => 15/224471 [patent_app_country] => US [patent_app_date] => 2016-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 20355 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15224471 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/224471
PARALLEL INSTRUCTION SCHEDULER FOR BLOCK ISA PROCESSOR Jul 28, 2016 Abandoned
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