Search

John M. Lindlof

Examiner (ID: 9223, Phone: (571)270-1024 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
489
Issued Applications
316
Pending Applications
30
Abandoned Applications
150

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13721431 [patent_doc_number] => 20170371670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => STREAM BASED BRANCH PREDICTION INDEX ACCELERATOR FOR MULTIPLE STREAM EXITS [patent_app_type] => utility [patent_app_number] => 15/193297 [patent_app_country] => US [patent_app_date] => 2016-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12031 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193297 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/193297
Stream based branch prediction index accelerator for multiple stream exits Jun 26, 2016 Issued
Array ( [id] => 13721407 [patent_doc_number] => 20170371658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => MANAGING A DIVIDED LOAD REORDER QUEUE [patent_app_type] => utility [patent_app_number] => 15/193338 [patent_app_country] => US [patent_app_date] => 2016-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8080 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193338 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/193338
Managing a divided load reorder queue Jun 26, 2016 Issued
Array ( [id] => 13721433 [patent_doc_number] => 20170371671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => STREAM BASED BRANCH PREDICTION INDEX ACCELERATOR WITH POWER PREDICTION [patent_app_type] => utility [patent_app_number] => 15/193304 [patent_app_country] => US [patent_app_date] => 2016-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12224 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193304 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/193304
Stream based branch prediction index accelerator with power prediction Jun 26, 2016 Issued
15/192537 HARDWARE COMPRESSION AND DECOMPRESSION ENGINE Jun 23, 2016
Array ( [id] => 11069940 [patent_doc_number] => 20160266904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'INSTRUCTION TO LOAD DATA UP TO A DYNAMICALLY DETERMINED MEMORY BOUNDARY' [patent_app_type] => utility [patent_app_number] => 15/163348 [patent_app_country] => US [patent_app_date] => 2016-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 17164 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15163348 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/163348
Instruction to load data up to a dynamically determined memory boundary May 23, 2016 Issued
Array ( [id] => 12372699 [patent_doc_number] => 09959118 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-01 [patent_title] => Instruction to load data up to a dynamically determined memory boundary [patent_app_type] => utility [patent_app_number] => 15/163161 [patent_app_country] => US [patent_app_date] => 2016-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 12310 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15163161 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/163161
Instruction to load data up to a dynamically determined memory boundary May 23, 2016 Issued
Array ( [id] => 12591372 [patent_doc_number] => 20180088953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => A PROCESSOR SYSTEM AND METHOD BASED ON INSTRUCTION AND DATA PUSH [patent_app_type] => utility [patent_app_number] => 15/568715 [patent_app_country] => US [patent_app_date] => 2016-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33886 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15568715 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/568715
A PROCESSOR SYSTEM AND METHOD BASED ON INSTRUCTION AND DATA PUSH Apr 21, 2016 Abandoned
Array ( [id] => 16683261 [patent_doc_number] => 10942739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-09 [patent_title] => Check instruction for verifying correct code execution context [patent_app_type] => utility [patent_app_number] => 15/571952 [patent_app_country] => US [patent_app_date] => 2016-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6851 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15571952 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/571952
Check instruction for verifying correct code execution context Apr 11, 2016 Issued
Array ( [id] => 17269152 [patent_doc_number] => 11194577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-07 [patent_title] => Instruction issue according to in-order or out-of-order execution modes [patent_app_type] => utility [patent_app_number] => 15/571915 [patent_app_country] => US [patent_app_date] => 2016-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3594 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15571915 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/571915
Instruction issue according to in-order or out-of-order execution modes Apr 10, 2016 Issued
Array ( [id] => 12796963 [patent_doc_number] => 20180157490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => VARIABLE-LENGTH-INSTRUCTION PROCESSING MODES [patent_app_type] => utility [patent_app_number] => 15/572678 [patent_app_country] => US [patent_app_date] => 2016-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15572678 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/572678
Variable-length-instruction processing modes Apr 6, 2016 Issued
Array ( [id] => 11278688 [patent_doc_number] => 09495167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-15 [patent_title] => 'Load queue entry reuse for operand store compare history table update' [patent_app_type] => utility [patent_app_number] => 15/080848 [patent_app_country] => US [patent_app_date] => 2016-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4696 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15080848 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/080848
Load queue entry reuse for operand store compare history table update Mar 24, 2016 Issued
Array ( [id] => 12611763 [patent_doc_number] => 20180095751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => PLACEMENT OF A CALCULATION TASK ON A FUNCTIONALLY ASYMMETRIC PROCESSOR [patent_app_type] => utility [patent_app_number] => 15/567067 [patent_app_country] => US [patent_app_date] => 2016-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8530 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15567067 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/567067
PLACEMENT OF A CALCULATION TASK ON A FUNCTIONALLY ASYMMETRIC PROCESSOR Mar 13, 2016 Abandoned
Array ( [id] => 11516263 [patent_doc_number] => 20170083338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'PREFETCHING ASSOCIATED WITH PREDICATED LOAD INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 15/061370 [patent_app_country] => US [patent_app_date] => 2016-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 27718 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15061370 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/061370
PREFETCHING ASSOCIATED WITH PREDICATED LOAD INSTRUCTIONS Mar 3, 2016 Abandoned
Array ( [id] => 11516265 [patent_doc_number] => 20170083339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'PREFETCHING ASSOCIATED WITH PREDICATED STORE INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 15/061408 [patent_app_country] => US [patent_app_date] => 2016-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 27896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15061408 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/061408
PREFETCHING ASSOCIATED WITH PREDICATED STORE INSTRUCTIONS Mar 3, 2016 Abandoned
Array ( [id] => 11077953 [patent_doc_number] => 20160274916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'PROCESSOR, PROGRAM CODE TRANSLATOR AND SOFTWARE' [patent_app_type] => utility [patent_app_number] => 15/056952 [patent_app_country] => US [patent_app_date] => 2016-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 17002 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15056952 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/056952
PROCESSOR, PROGRAM CODE TRANSLATOR AND SOFTWARE Feb 28, 2016 Abandoned
Array ( [id] => 11944998 [patent_doc_number] => 20170249149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'DYNAMIC PIPELINE THROTTLING USING CONFIDENCE-BASED WEIGHTING OF IN-FLIGHT BRANCH INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 15/057116 [patent_app_country] => US [patent_app_date] => 2016-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6081 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15057116 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/057116
Dynamic pipeline throttling using confidence-based weighting of in-flight branch instructions Feb 28, 2016 Issued
Array ( [id] => 13017273 [patent_doc_number] => 10031751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Arithmetic processing device and method for controlling arithmetic processing device [patent_app_type] => utility [patent_app_number] => 15/056495 [patent_app_country] => US [patent_app_date] => 2016-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8616 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15056495 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/056495
Arithmetic processing device and method for controlling arithmetic processing device Feb 28, 2016 Issued
Array ( [id] => 14669197 [patent_doc_number] => 10372500 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-06 [patent_title] => Register allocation system [patent_app_type] => utility [patent_app_number] => 15/046364 [patent_app_country] => US [patent_app_date] => 2016-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10355 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15046364 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/046364
Register allocation system Feb 16, 2016 Issued
Array ( [id] => 11868292 [patent_doc_number] => 20170235577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING A MECHANISM TO OVERCOME A SYSTEM HANG' [patent_app_type] => utility [patent_app_number] => 15/042902 [patent_app_country] => US [patent_app_date] => 2016-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6875 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15042902 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/042902
Operation of a multi-slice processor implementing a mechanism to overcome a system hang Feb 11, 2016 Issued
Array ( [id] => 11403674 [patent_doc_number] => 20170024212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-26 [patent_title] => 'HARDWARE ACCELERATION COMPONENTS FOR TRANSLATING GUEST INSTRUCTIONS TO NATIVE INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 15/042005 [patent_app_country] => US [patent_app_date] => 2016-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11474 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15042005 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/042005
HARDWARE ACCELERATION COMPONENTS FOR TRANSLATING GUEST INSTRUCTIONS TO NATIVE INSTRUCTIONS Feb 10, 2016 Abandoned
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