Search

John M. Parker

Examiner (ID: 11130, Phone: (571)272-8794 , Office: P/2816 )

Most Active Art Unit
2816
Art Unit(s)
2899, 2823, 2816
Total Applications
1173
Issued Applications
1023
Pending Applications
77
Abandoned Applications
108

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19138000 [patent_doc_number] => 11972975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Semiconductor device structure having air gap and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/356959 [patent_app_country] => US [patent_app_date] => 2021-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5882 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17356959 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/356959
Semiconductor device structure having air gap and method for forming the same Jun 23, 2021 Issued
Array ( [id] => 18898561 [patent_doc_number] => 20240014046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => METHOD AND DEVICE FOR MAKING INTEGRATED COOLING LIQUID CAVITY IN PRINTED CIRCUIT BOARD [patent_app_type] => utility [patent_app_number] => 18/036281 [patent_app_country] => US [patent_app_date] => 2021-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18036281 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/036281
METHOD AND DEVICE FOR MAKING INTEGRATED COOLING LIQUID CAVITY IN PRINTED CIRCUIT BOARD Jun 15, 2021 Pending
Array ( [id] => 19168438 [patent_doc_number] => 11984351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Cavity in metal interconnect structure [patent_app_type] => utility [patent_app_number] => 17/346670 [patent_app_country] => US [patent_app_date] => 2021-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 45 [patent_no_of_words] => 9593 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17346670 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/346670
Cavity in metal interconnect structure Jun 13, 2021 Issued
Array ( [id] => 17551664 [patent_doc_number] => 20220123006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/340148 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13415 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340148 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/340148
Semiconductor memory device and electronic system including the same Jun 6, 2021 Issued
Array ( [id] => 18935446 [patent_doc_number] => 11887889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Semiconductor device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/336539 [patent_app_country] => US [patent_app_date] => 2021-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2265 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17336539 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/336539
Semiconductor device and method for manufacturing the same Jun 1, 2021 Issued
Array ( [id] => 18334516 [patent_doc_number] => 20230126464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/615059 [patent_app_country] => US [patent_app_date] => 2021-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5742 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17615059 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/615059
Semiconductor device and manufacturing method thereof May 23, 2021 Issued
Array ( [id] => 18507536 [patent_doc_number] => 11705363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Fully aligned via integration with selective catalyzed vapor phase grown materials [patent_app_type] => utility [patent_app_number] => 17/326973 [patent_app_country] => US [patent_app_date] => 2021-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5709 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17326973 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/326973
Fully aligned via integration with selective catalyzed vapor phase grown materials May 20, 2021 Issued
Array ( [id] => 19812412 [patent_doc_number] => 12243825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Hybrid conductive vias for electronic substrates [patent_app_type] => utility [patent_app_number] => 17/326569 [patent_app_country] => US [patent_app_date] => 2021-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 8153 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17326569 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/326569
Hybrid conductive vias for electronic substrates May 20, 2021 Issued
Array ( [id] => 18024383 [patent_doc_number] => 20220375882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => MICROELECTRONIC ASSEMBLIES HAVING INTEGRATED MAGNETIC CORE INDUCTORS [patent_app_type] => utility [patent_app_number] => 17/323194 [patent_app_country] => US [patent_app_date] => 2021-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17323194 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/323194
Microelectronic assemblies having integrated magnetic core inductors May 17, 2021 Issued
Array ( [id] => 18008598 [patent_doc_number] => 20220367365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => ELECTRONIC DEVICES AND METHODS OF MANUFACTURING ELECTRONIC DEVICES [patent_app_type] => utility [patent_app_number] => 17/318179 [patent_app_country] => US [patent_app_date] => 2021-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5896 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318179 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/318179
Electronic devices and methods of manufacturing electronic devices May 11, 2021 Issued
Array ( [id] => 17509129 [patent_doc_number] => 20220102232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => SEMICONDUCTOR PACKAGING STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/318066 [patent_app_country] => US [patent_app_date] => 2021-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3657 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318066 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/318066
Semiconductor packaging structure May 11, 2021 Issued
Array ( [id] => 17993315 [patent_doc_number] => 20220359352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => ELECTRONIC PACKAGE WITH CONCAVE LEAD END FACES [patent_app_type] => utility [patent_app_number] => 17/316703 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17316703 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/316703
ELECTRONIC PACKAGE WITH CONCAVE LEAD END FACES May 9, 2021 Pending
Array ( [id] => 17993244 [patent_doc_number] => 20220359281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => METHODS OF FORMING MOLYBDENUM CONTACTS [patent_app_type] => utility [patent_app_number] => 17/314515 [patent_app_country] => US [patent_app_date] => 2021-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17314515 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/314515
Methods of forming molybdenum contacts May 6, 2021 Issued
Array ( [id] => 17738074 [patent_doc_number] => 20220223536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => REDISTRIBUTION LAYER FEATURES [patent_app_type] => utility [patent_app_number] => 17/308321 [patent_app_country] => US [patent_app_date] => 2021-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17308321 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/308321
Redistribution layer features May 4, 2021 Issued
Array ( [id] => 17025578 [patent_doc_number] => 20210249450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/243817 [patent_app_country] => US [patent_app_date] => 2021-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4530 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17243817 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/243817
Array substrate, method for manufacturing the same, and display device Apr 28, 2021 Issued
Array ( [id] => 18528684 [patent_doc_number] => 11715687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Contact structures for reducing electrical shorts and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/232623 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 8022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17232623 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/232623
Contact structures for reducing electrical shorts and methods of forming the same Apr 15, 2021 Issued
Array ( [id] => 18782312 [patent_doc_number] => 11824079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Thin-film resistor (TFR) having a TFR element providing a diffusion barrier for underlying TFR heads [patent_app_type] => utility [patent_app_number] => 17/233285 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 7836 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17233285 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/233285
Thin-film resistor (TFR) having a TFR element providing a diffusion barrier for underlying TFR heads Apr 15, 2021 Issued
Array ( [id] => 19842788 [patent_doc_number] => 12255189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Secure semiconductor integration and method for making thereof [patent_app_type] => utility [patent_app_number] => 17/229866 [patent_app_country] => US [patent_app_date] => 2021-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 39 [patent_no_of_words] => 5689 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17229866 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/229866
Secure semiconductor integration and method for making thereof Apr 13, 2021 Issued
Array ( [id] => 16981520 [patent_doc_number] => 20210225757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => CO-INTEGRATED VERTICALLY STRUCTURED CAPACITIVE ELEMENT AND FABRICATION PROCESS [patent_app_type] => utility [patent_app_number] => 17/226324 [patent_app_country] => US [patent_app_date] => 2021-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5397 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17226324 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/226324
Co-integrated vertically structured capacitive element and fabrication process Apr 8, 2021 Issued
Array ( [id] => 18759937 [patent_doc_number] => 11810977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Semiconductor device with embedded sigma-shaped structure [patent_app_type] => utility [patent_app_number] => 17/219195 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6975 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219195 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/219195
Semiconductor device with embedded sigma-shaped structure Mar 30, 2021 Issued
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