Search

John M. Parker

Examiner (ID: 11130, Phone: (571)272-8794 , Office: P/2816 )

Most Active Art Unit
2816
Art Unit(s)
2899, 2823, 2816
Total Applications
1173
Issued Applications
1023
Pending Applications
77
Abandoned Applications
108

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18047949 [patent_doc_number] => 11521907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Hybrid embedded package [patent_app_type] => utility [patent_app_number] => 17/070559 [patent_app_country] => US [patent_app_date] => 2020-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5947 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17070559 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/070559
Hybrid embedded package Oct 13, 2020 Issued
Array ( [id] => 16586088 [patent_doc_number] => 20210020490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => SUPPORT SUBSTRATES, METHODS OF FABRICATING SEMICONDUCTOR PACKAGES USING THE SAME, AND METHODS OF FABRICATING ELECTRONIC DEVICES USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/060800 [patent_app_country] => US [patent_app_date] => 2020-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17060800 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/060800
Support substrates, methods of fabricating semiconductor packages using the same, and methods of fabricating electronic devices using the same Sep 30, 2020 Issued
Array ( [id] => 17509098 [patent_doc_number] => 20220102201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => ADDITIVE DAMASCENE PROCESS [patent_app_type] => utility [patent_app_number] => 17/035569 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4675 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17035569 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/035569
ADDITIVE DAMASCENE PROCESS Sep 27, 2020 Abandoned
Array ( [id] => 18120569 [patent_doc_number] => 11551968 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Inter-wire cavity for low capacitance [patent_app_type] => utility [patent_app_number] => 17/029213 [patent_app_country] => US [patent_app_date] => 2020-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 45 [patent_no_of_words] => 10993 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17029213 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/029213
Inter-wire cavity for low capacitance Sep 22, 2020 Issued
Array ( [id] => 16560563 [patent_doc_number] => 20210005712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => Transistor devices having source/drain structure configured with high germanium content portion [patent_app_type] => utility [patent_app_number] => 17/025077 [patent_app_country] => US [patent_app_date] => 2020-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9463 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17025077 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/025077
Column IV transistors for PMOS integration Sep 17, 2020 Issued
Array ( [id] => 17978896 [patent_doc_number] => 11495773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Display device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/019458 [patent_app_country] => US [patent_app_date] => 2020-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8814 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17019458 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/019458
Display device and manufacturing method thereof Sep 13, 2020 Issued
Array ( [id] => 16920421 [patent_doc_number] => 20210193513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => SELECTIVE DEPOSITION OF A PROTECTIVE LAYER TO REDUCE INTERCONNECT STRUCTURE CRITICAL DIMENSIONS [patent_app_type] => utility [patent_app_number] => 17/012427 [patent_app_country] => US [patent_app_date] => 2020-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17012427 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/012427
Selective deposition of a protective layer to reduce interconnect structure critical dimensions Sep 3, 2020 Issued
Array ( [id] => 18054083 [patent_doc_number] => 11527477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-13 [patent_title] => Semiconductor device and method of manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 17/010449 [patent_app_country] => US [patent_app_date] => 2020-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 8872 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17010449 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/010449
Semiconductor device and method of manufacturing semiconductor device Sep 1, 2020 Issued
Array ( [id] => 18447040 [patent_doc_number] => 11682616 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Semiconductor structure and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/008141 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 9028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17008141 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/008141
Semiconductor structure and method for forming the same Aug 30, 2020 Issued
Array ( [id] => 16509436 [patent_doc_number] => 20200388692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/001501 [patent_app_country] => US [patent_app_date] => 2020-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17001501 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/001501
Semiconductor device and method of manufacturing the same Aug 23, 2020 Issued
Array ( [id] => 18796981 [patent_doc_number] => 11830816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Reduced resistivity for access lines in a memory array [patent_app_type] => utility [patent_app_number] => 16/993695 [patent_app_country] => US [patent_app_date] => 2020-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10739 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16993695 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/993695
Reduced resistivity for access lines in a memory array Aug 13, 2020 Issued
Array ( [id] => 16881203 [patent_doc_number] => 11031360 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Techniques for an inductor at a second level interface [patent_app_type] => utility [patent_app_number] => 16/990782 [patent_app_country] => US [patent_app_date] => 2020-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4841 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16990782 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/990782
Techniques for an inductor at a second level interface Aug 10, 2020 Issued
Array ( [id] => 18054069 [patent_doc_number] => 11527463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-13 [patent_title] => Hybrid ball grid array package for high speed interconnects [patent_app_type] => utility [patent_app_number] => 16/984173 [patent_app_country] => US [patent_app_date] => 2020-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6730 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16984173 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/984173
Hybrid ball grid array package for high speed interconnects Aug 3, 2020 Issued
Array ( [id] => 17389548 [patent_doc_number] => 20220037400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => ON-PITCH VIAS FOR SEMICONDUCTOR DEVICES AND ASSOCIATED DEVICES AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/983843 [patent_app_country] => US [patent_app_date] => 2020-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7297 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16983843 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/983843
On-pitch vias for semiconductor devices and associated devices and systems Aug 2, 2020 Issued
Array ( [id] => 16456023 [patent_doc_number] => 20200365449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => Metal Routing with Flexible Space Formed Using Self-Aligned Spacer Patterning [patent_app_type] => utility [patent_app_number] => 16/983475 [patent_app_country] => US [patent_app_date] => 2020-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16983475 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/983475
Metal routing with flexible space formed using self-aligned spacer patterning Aug 2, 2020 Issued
Array ( [id] => 17010917 [patent_doc_number] => 20210242078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/943815 [patent_app_country] => US [patent_app_date] => 2020-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8851 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16943815 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/943815
Semiconductor structure and method for forming the same Jul 29, 2020 Issued
Array ( [id] => 17389338 [patent_doc_number] => 20220037190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/943996 [patent_app_country] => US [patent_app_date] => 2020-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16943996 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/943996
Semiconductor device structure and methods of forming the same Jul 29, 2020 Issued
Array ( [id] => 17389351 [patent_doc_number] => 20220037203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => THERMALLY STABLE COPPER-ALLOY ADHESION LAYER FOR METAL INTERCONNECT STRUCTURES AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/941751 [patent_app_country] => US [patent_app_date] => 2020-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16941751 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/941751
Thermally stable copper-alloy adhesion layer for metal interconnect structures and methods for forming the same Jul 28, 2020 Issued
Array ( [id] => 17365950 [patent_doc_number] => 11232981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => Semiconductor device and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 16/940730 [patent_app_country] => US [patent_app_date] => 2020-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5222 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16940730 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/940730
Semiconductor device and fabrication method thereof Jul 27, 2020 Issued
Array ( [id] => 17055807 [patent_doc_number] => 20210265241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => FRONT-END-OF-LINE (FEOL) THROUGH SEMICONDUCTOR-ON-SUBSTRATE VIA (TSV) [patent_app_type] => utility [patent_app_number] => 16/936654 [patent_app_country] => US [patent_app_date] => 2020-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11334 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16936654 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/936654
Front-end-of-line (FEOL) through semiconductor-on-substrate via (TSV) Jul 22, 2020 Issued
Menu