Search

John M. Parker

Examiner (ID: 11130, Phone: (571)272-8794 , Office: P/2816 )

Most Active Art Unit
2816
Art Unit(s)
2899, 2823, 2816
Total Applications
1173
Issued Applications
1023
Pending Applications
77
Abandoned Applications
108

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17825781 [patent_doc_number] => 11430735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Barrier removal for conductor in top via integration scheme [patent_app_type] => utility [patent_app_number] => 16/791400 [patent_app_country] => US [patent_app_date] => 2020-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4094 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16791400 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/791400
Barrier removal for conductor in top via integration scheme Feb 13, 2020 Issued
Array ( [id] => 16812385 [patent_doc_number] => 20210134940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => RING STRUCTURE FOR FILM RESISTOR [patent_app_type] => utility [patent_app_number] => 16/789839 [patent_app_country] => US [patent_app_date] => 2020-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16789839 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/789839
Ring structure for film resistor Feb 12, 2020 Issued
Array ( [id] => 17025478 [patent_doc_number] => 20210249350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => Process for Forming Metal-Insulator-Metal Structures [patent_app_type] => utility [patent_app_number] => 16/787933 [patent_app_country] => US [patent_app_date] => 2020-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8066 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16787933 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/787933
Process for forming metal-insulator-metal structures Feb 10, 2020 Issued
Array ( [id] => 16593736 [patent_doc_number] => 10903013 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Dielectric powder and multilayer capacitor using the same [patent_app_type] => utility [patent_app_number] => 16/782586 [patent_app_country] => US [patent_app_date] => 2020-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4404 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16782586 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/782586
Dielectric powder and multilayer capacitor using the same Feb 4, 2020 Issued
Array ( [id] => 17010921 [patent_doc_number] => 20210242082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => INTERCONNECT STRUCTURES WITH COBALT-INFUSED RUTHENIUM LINER AND A COBALT CAP [patent_app_type] => utility [patent_app_number] => 16/781038 [patent_app_country] => US [patent_app_date] => 2020-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4932 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16781038 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/781038
Interconnect structures with cobalt-infused ruthenium liner and a cobalt cap Feb 3, 2020 Issued
Array ( [id] => 17439052 [patent_doc_number] => 11264393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Source/drain contact having a protruding segment [patent_app_type] => utility [patent_app_number] => 16/776205 [patent_app_country] => US [patent_app_date] => 2020-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10238 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16776205 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/776205
Source/drain contact having a protruding segment Jan 28, 2020 Issued
Array ( [id] => 16995431 [patent_doc_number] => 20210233851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => METHODS FOR MAKING DOUBLE-SIDED SEMICONDUCTOR DEVICES AND RELATED DEVICES, ASSEMBLIES, PACKAGES AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/751676 [patent_app_country] => US [patent_app_date] => 2020-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10395 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16751676 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/751676
Methods for making double-sided semiconductor devices and related devices, assemblies, packages and systems Jan 23, 2020 Issued
Array ( [id] => 16560384 [patent_doc_number] => 20210005533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => SEMICONDUCTOR PACKAGES INCLUDING THROUGH HOLES AND METHODS OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/750579 [patent_app_country] => US [patent_app_date] => 2020-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16750579 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/750579
Semiconductor packages including through holes and methods of fabricating the same Jan 22, 2020 Issued
Array ( [id] => 17395855 [patent_doc_number] => 11244879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 16/746976 [patent_app_country] => US [patent_app_date] => 2020-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 29 [patent_no_of_words] => 10918 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16746976 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/746976
Semiconductor package Jan 19, 2020 Issued
Array ( [id] => 16981454 [patent_doc_number] => 20210225691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => INTERCONNECTS WITH SPACER STRUCTURE FOR FORMING AIR-GAPS [patent_app_type] => utility [patent_app_number] => 16/744912 [patent_app_country] => US [patent_app_date] => 2020-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4591 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16744912 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/744912
Interconnects with spacer structure for forming air-gaps Jan 15, 2020 Issued
Array ( [id] => 16981465 [patent_doc_number] => 20210225702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => REMOVAL OF BARRIER AND LINER LAYERS FROM A BOTTOM OF A VIA [patent_app_type] => utility [patent_app_number] => 16/744984 [patent_app_country] => US [patent_app_date] => 2020-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5189 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16744984 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/744984
Removal of barrier and liner layers from a bottom of a via Jan 15, 2020 Issued
Array ( [id] => 17700246 [patent_doc_number] => 11373980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 16/744623 [patent_app_country] => US [patent_app_date] => 2020-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 4574 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16744623 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/744623
Semiconductor package Jan 15, 2020 Issued
Array ( [id] => 17623157 [patent_doc_number] => 11342221 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/741187 [patent_app_country] => US [patent_app_date] => 2020-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 11272 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16741187 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/741187
Semiconductor device Jan 12, 2020 Issued
Array ( [id] => 16668484 [patent_doc_number] => 10937742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Package and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/739053 [patent_app_country] => US [patent_app_date] => 2020-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8387 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16739053 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/739053
Package and manufacturing method thereof Jan 8, 2020 Issued
Array ( [id] => 16163227 [patent_doc_number] => 20200219846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => MULTI-CHIP PACKAGE POWER MODULE [patent_app_type] => utility [patent_app_number] => 16/735716 [patent_app_country] => US [patent_app_date] => 2020-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12191 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16735716 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/735716
Multi-chip package power module Jan 6, 2020 Issued
Array ( [id] => 15874047 [patent_doc_number] => 20200144427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => VERTICAL SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/735273 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11360 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16735273 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/735273
Vertical semiconductor devices Jan 5, 2020 Issued
Array ( [id] => 16218453 [patent_doc_number] => 10734275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Metal routing with flexible space formed using self-aligned spacer patterning [patent_app_type] => utility [patent_app_number] => 16/727593 [patent_app_country] => US [patent_app_date] => 2019-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 43 [patent_no_of_words] => 7189 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16727593 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/727593
Metal routing with flexible space formed using self-aligned spacer patterning Dec 25, 2019 Issued
Array ( [id] => 17683412 [patent_doc_number] => 11367677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-21 [patent_title] => Electronic component module [patent_app_type] => utility [patent_app_number] => 16/724422 [patent_app_country] => US [patent_app_date] => 2019-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 25 [patent_no_of_words] => 9842 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16724422 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/724422
Electronic component module Dec 22, 2019 Issued
Array ( [id] => 15841241 [patent_doc_number] => 20200135903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => METHOD OF FORMING SHAPED SOURCE/DRAIN EPITAXIAL LAYERS OF A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/725655 [patent_app_country] => US [patent_app_date] => 2019-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5551 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16725655 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/725655
Method of forming shaped source/drain epitaxial layers of a semiconductor device Dec 22, 2019 Issued
Array ( [id] => 16920486 [patent_doc_number] => 20210193578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/721664 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7540 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16721664 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/721664
Semiconductor package structure and method for manufacturing the same Dec 18, 2019 Issued
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