John M. Parker

Array ( [id] => 16936378 [patent_doc_number] => 20210202267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => TIE BAR REMOVAL FOR SEMICONDUCTOR DEVICE PACKAGING [patent_app_type] => utility [patent_app_number] => 16/862027 [patent_app_country] => US [patent_app_date] => 2020-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3656 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16862027 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17456041 [patent_doc_number] => 11270908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-08 [patent_title] => Semiconductor die structure with air gaps and method for preparing the same [patent_app_type] => utility [patent_app_number] => 16/855601 [patent_app_country] => US [patent_app_date] => 2020-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6767 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16855601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16226266 [patent_doc_number] => 20200251383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/851191 [patent_app_country] => US [patent_app_date] => 2020-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4557 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16851191 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16617261 [patent_doc_number] => 20210035914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => CHIP PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/849999 [patent_app_country] => US [patent_app_date] => 2020-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4871 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16849999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17239564 [patent_doc_number] => 11183455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Interconnects with enlarged contact area [patent_app_type] => utility [patent_app_number] => 16/849342 [patent_app_country] => US [patent_app_date] => 2020-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 24 [patent_no_of_words] => 6228 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16849342 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17181513 [patent_doc_number] => 11158764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => Epitaxial formation support structures and associated methods [patent_app_type] => utility [patent_app_number] => 16/846137 [patent_app_country] => US [patent_app_date] => 2020-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3960 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16846137 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17310165 [patent_doc_number] => 11211291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Via formation with robust hardmask removal [patent_app_type] => utility [patent_app_number] => 16/839863 [patent_app_country] => US [patent_app_date] => 2020-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7068 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16839863 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17145249 [patent_doc_number] => 20210313262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => Hybrid Method for Forming Semiconductor Interconnect Structure [patent_app_type] => utility [patent_app_number] => 16/837762 [patent_app_country] => US [patent_app_date] => 2020-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9707 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16837762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17145255 [patent_doc_number] => 20210313268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => ADVANCED NODE INTERCONNECT ROUTING METHODOLOGY [patent_app_type] => utility [patent_app_number] => 16/837795 [patent_app_country] => US [patent_app_date] => 2020-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15630 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16837795 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16339496 [patent_doc_number] => 10790467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => Display device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/836005 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 11283 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16836005 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17787796 [patent_doc_number] => 11410932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Semiconductor device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/833684 [patent_app_country] => US [patent_app_date] => 2020-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 16633 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16833684 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16163445 [patent_doc_number] => 20200219955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/824323 [patent_app_country] => US [patent_app_date] => 2020-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3966 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16824323 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17668282 [patent_doc_number] => 11361986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-14 [patent_title] => Using a liner layer to enlarge process window for a contact via [patent_app_type] => utility [patent_app_number] => 16/808902 [patent_app_country] => US [patent_app_date] => 2020-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 63 [patent_no_of_words] => 14318 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16808902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16677434 [patent_doc_number] => 20210066200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 16/802676 [patent_app_country] => US [patent_app_date] => 2020-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10943 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16802676 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19958544 [patent_doc_number] => 12328975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-10 [patent_title] => Optoelectronic semiconductor structure comprising a p-type injection layer based on InGaN [patent_app_type] => utility [patent_app_number] => 17/435014 [patent_app_country] => US [patent_app_date] => 2020-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 0 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17435014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16904867 [patent_doc_number] => 20210183783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => SUBSTRATE WITH ELECTRONIC COMPONENT EMBEDDED THEREIN [patent_app_type] => utility [patent_app_number] => 16/795985 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16795985 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17529930 [patent_doc_number] => 11302629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => Semiconductor device with composite passivation structure and method for preparing the same [patent_app_type] => utility [patent_app_number] => 16/794758 [patent_app_country] => US [patent_app_date] => 2020-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7680 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16794758 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16372339 [patent_doc_number] => 10804105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Semiconductor device and manufacture thereof [patent_app_type] => utility [patent_app_number] => 16/794757 [patent_app_country] => US [patent_app_date] => 2020-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 6453 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16794757 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17040663 [patent_doc_number] => 20210257299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => HYBRID INTERCONNECT WITH A RELIABILITY LINER IN WIDE FEATURES [patent_app_type] => utility [patent_app_number] => 16/793883 [patent_app_country] => US [patent_app_date] => 2020-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4728 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16793883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17825781 [patent_doc_number] => 11430735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Barrier removal for conductor in top via integration scheme [patent_app_type] => utility [patent_app_number] => 16/791400 [patent_app_country] => US [patent_app_date] => 2020-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4094 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16791400 [rel_patent_id] =>[rel_patent_doc_number] =>)