Search

John M. Parker

Examiner (ID: 11130, Phone: (571)272-8794 , Office: P/2816 )

Most Active Art Unit
2816
Art Unit(s)
2899, 2823, 2816
Total Applications
1173
Issued Applications
1023
Pending Applications
77
Abandoned Applications
108

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19007871 [patent_doc_number] => 20240071942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/120826 [patent_app_country] => US [patent_app_date] => 2023-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18120826 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/120826
SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME Mar 12, 2023 Pending
Array ( [id] => 19436054 [patent_doc_number] => 20240304552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => SEMICONDUCTOR DEVICE WITH FILLING LAYER [patent_app_type] => utility [patent_app_number] => 18/119947 [patent_app_country] => US [patent_app_date] => 2023-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9831 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18119947 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/119947
SEMICONDUCTOR DEVICE WITH FILLING LAYER Mar 9, 2023 Pending
Array ( [id] => 18789315 [patent_doc_number] => 20230377968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => REDISTRIBUTION LAYER METALLIC STRUCTURE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/181293 [patent_app_country] => US [patent_app_date] => 2023-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9048 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18181293 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/181293
REDISTRIBUTION LAYER METALLIC STRUCTURE AND METHOD Mar 8, 2023 Pending
Array ( [id] => 18500538 [patent_doc_number] => 20230223332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => CO-INTEGRATED VERTICALLY STRUCTURED CAPACITIVE ELEMENT AND FABRICATION PROCESS [patent_app_type] => utility [patent_app_number] => 18/118935 [patent_app_country] => US [patent_app_date] => 2023-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5414 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18118935 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/118935
Co-integrated vertically structured capacitive element and fabrication process Mar 7, 2023 Issued
Array ( [id] => 20484253 [patent_doc_number] => 12532734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Semiconductor device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 18/179377 [patent_app_country] => US [patent_app_date] => 2023-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 1181 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18179377 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/179377
Semiconductor device and method of fabricating the same Mar 6, 2023 Issued
Array ( [id] => 19071166 [patent_doc_number] => 20240105592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => ISOLATOR [patent_app_type] => utility [patent_app_number] => 18/178448 [patent_app_country] => US [patent_app_date] => 2023-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4535 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18178448 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/178448
Isolator Mar 2, 2023 Issued
Array ( [id] => 19421043 [patent_doc_number] => 20240297167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => SELF-ALIGNED BACKSIDE INTERCONNECT STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/176551 [patent_app_country] => US [patent_app_date] => 2023-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18176551 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/176551
SELF-ALIGNED BACKSIDE INTERCONNECT STRUCTURES Feb 28, 2023 Pending
Array ( [id] => 19364176 [patent_doc_number] => 20240266210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => Semiconductor circuit pattern and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/116276 [patent_app_country] => US [patent_app_date] => 2023-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18116276 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/116276
Semiconductor circuit pattern and manufacturing method thereof Feb 28, 2023 Pending
Array ( [id] => 20244215 [patent_doc_number] => 12424546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Semiconductor structure and method for forming same [patent_app_type] => utility [patent_app_number] => 18/176652 [patent_app_country] => US [patent_app_date] => 2023-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 45 [patent_no_of_words] => 9081 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18176652 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/176652
Semiconductor structure and method for forming same Feb 28, 2023 Issued
Array ( [id] => 18848891 [patent_doc_number] => 20230411295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME [patent_app_type] => utility [patent_app_number] => 18/176904 [patent_app_country] => US [patent_app_date] => 2023-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18176904 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/176904
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME Feb 28, 2023 Pending
Array ( [id] => 19407177 [patent_doc_number] => 20240290688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => SUPER VIA WITHIN BACKSIDE LEVEL [patent_app_type] => utility [patent_app_number] => 18/175903 [patent_app_country] => US [patent_app_date] => 2023-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11695 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18175903 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/175903
SUPER VIA WITHIN BACKSIDE LEVEL Feb 27, 2023 Pending
Array ( [id] => 20260590 [patent_doc_number] => 12432961 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Integrated structure of MOS transistors having different working voltages and method for manufacturing same [patent_app_type] => utility [patent_app_number] => 18/174767 [patent_app_country] => US [patent_app_date] => 2023-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2096 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 369 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18174767 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/174767
Integrated structure of MOS transistors having different working voltages and method for manufacturing same Feb 26, 2023 Issued
Array ( [id] => 19146314 [patent_doc_number] => 20240145344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => VIA STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/172420 [patent_app_country] => US [patent_app_date] => 2023-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10096 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18172420 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/172420
VIA STRUCTURE AND METHOD FOR FORMING THE SAME Feb 21, 2023 Pending
Array ( [id] => 19038165 [patent_doc_number] => 20240087980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => ETCHING-DAMAGE-FREE INTERMETAL DIELECTRIC LAYER WITH THERMAL DISSIPATION FEATURE [patent_app_type] => utility [patent_app_number] => 18/170933 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170933 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/170933
ETCHING-DAMAGE-FREE INTERMETAL DIELECTRIC LAYER WITH THERMAL DISSIPATION FEATURE Feb 16, 2023 Pending
Array ( [id] => 19392760 [patent_doc_number] => 20240282630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => SEMICONDUCTOR STRUCTURES INCLUDING METAL WIRES WITH EDGE CURVATURE [patent_app_type] => utility [patent_app_number] => 18/169984 [patent_app_country] => US [patent_app_date] => 2023-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6001 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18169984 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/169984
SEMICONDUCTOR STRUCTURES INCLUDING METAL WIRES WITH EDGE CURVATURE Feb 15, 2023 Pending
Array ( [id] => 18774382 [patent_doc_number] => 20230369213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => CONTACT ARRANGEMENTS FOR DEEP TRENCH CAPACITORS [patent_app_type] => utility [patent_app_number] => 18/169600 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9432 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18169600 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/169600
CONTACT ARRANGEMENTS FOR DEEP TRENCH CAPACITORS Feb 14, 2023 Pending
Array ( [id] => 18570498 [patent_doc_number] => 20230260835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => CONTACT FOR ELECTRONIC COMPONENT [patent_app_type] => utility [patent_app_number] => 18/109569 [patent_app_country] => US [patent_app_date] => 2023-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18109569 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/109569
CONTACT FOR ELECTRONIC COMPONENT Feb 13, 2023 Pending
Array ( [id] => 20509263 [patent_doc_number] => 12543556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Semiconductor devices and methods of forming the same [patent_app_type] => utility [patent_app_number] => 18/167087 [patent_app_country] => US [patent_app_date] => 2023-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 4372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18167087 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/167087
SEMICONDCUTOR DEVICES AND METHODS OF FORMING THE SAME Feb 9, 2023 Issued
Array ( [id] => 19269600 [patent_doc_number] => 20240213304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => MIM CAPACITOR STRUCTURE AND FABRICATING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 18/107521 [patent_app_country] => US [patent_app_date] => 2023-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18107521 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/107521
MIM capacitor structure and fabricating method of the same Feb 8, 2023 Issued
Array ( [id] => 18456510 [patent_doc_number] => 20230197792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => STRUCTURES WITH DOPED SEMICONDUCTOR LAYERS AND METHODS AND SYSTEMS FOR FORMING SAME [patent_app_type] => utility [patent_app_number] => 18/107688 [patent_app_country] => US [patent_app_date] => 2023-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10696 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18107688 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/107688
Structures with doped semiconductor layers and methods and systems for forming same Feb 8, 2023 Issued
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