John M. Parker

Array ( [id] => 20148396 [patent_doc_number] => 12382757 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Light emitting element [patent_app_type] => utility [patent_app_number] => 18/159279 [patent_app_country] => US [patent_app_date] => 2023-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1180 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18159279 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18379757 [patent_doc_number] => 20230154846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/156752 [patent_app_country] => US [patent_app_date] => 2023-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11559 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18156752 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20175914 [patent_doc_number] => 12394669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Wet cleaning with tunable metal recess for via plugs [patent_app_type] => utility [patent_app_number] => 18/153832 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1058 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18153832 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18379764 [patent_doc_number] => 20230154853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/153447 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18153447 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19086152 [patent_doc_number] => 20240112953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => METAL FILL STRUCTURES FOR ISOLATORS TO MEET METAL DENSITY AND HIGH VOLTAGE ELECTRIC FIELD REQUIREMENTS [patent_app_type] => utility [patent_app_number] => 18/148231 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18148231 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19269383 [patent_doc_number] => 20240213087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => ADVANCED PITCH INTERCONNECTS WITH MULTIPLE LOW ASPECT RATIO SEGMENTS [patent_app_type] => utility [patent_app_number] => 18/146478 [patent_app_country] => US [patent_app_date] => 2022-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18146478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19269388 [patent_doc_number] => 20240213092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => OCTAGONAL INTERCONNECT WIRING FOR ADVANCED LOGIC [patent_app_type] => utility [patent_app_number] => 18/145157 [patent_app_country] => US [patent_app_date] => 2022-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5913 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18145157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18320437 [patent_doc_number] => 20230118565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => HYBRID METHOD FOR FORMING SEMICONDUCTOR INTERCONNECT STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/066464 [patent_app_country] => US [patent_app_date] => 2022-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9753 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18066464 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19237329 [patent_doc_number] => 20240194524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => SEMICONDUCTOR DEVICE WITH A LINER LAYER [patent_app_type] => utility [patent_app_number] => 18/077382 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12605 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18077382 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19844177 [patent_doc_number] => 12256593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Display device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/073870 [patent_app_country] => US [patent_app_date] => 2022-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 11362 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18073870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18533235 [patent_doc_number] => 20230238311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/058705 [patent_app_country] => US [patent_app_date] => 2022-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7654 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18058705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20216143 [patent_doc_number] => 12412797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Hybrid embedded package [patent_app_type] => utility [patent_app_number] => 17/973920 [patent_app_country] => US [patent_app_date] => 2022-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 5 [patent_no_of_words] => 1187 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17973920 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20375342 [patent_doc_number] => 12482786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Hybrid wafer bonding method [patent_app_type] => utility [patent_app_number] => 17/963649 [patent_app_country] => US [patent_app_date] => 2022-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5600 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17963649 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18160423 [patent_doc_number] => 20230027015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => HYBRID WAFER BONDING METHOD AND STRUCTURE THEREOF [patent_app_type] => utility [patent_app_number] => 17/958764 [patent_app_country] => US [patent_app_date] => 2022-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958764 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19859706 [patent_doc_number] => 12262583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Display device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/953463 [patent_app_country] => US [patent_app_date] => 2022-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8842 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17953463 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18140099 [patent_doc_number] => 20230013938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/947288 [patent_app_country] => US [patent_app_date] => 2022-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17947288 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19582501 [patent_doc_number] => 12148628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Semiconductor device and corresponding method [patent_app_type] => utility [patent_app_number] => 17/942843 [patent_app_country] => US [patent_app_date] => 2022-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2616 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17942843 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18097460 [patent_doc_number] => 20220415801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => INTERCONNECT STRUCTURE AND ELECTRONIC APPARATUS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/902319 [patent_app_country] => US [patent_app_date] => 2022-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17902319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18113111 [patent_doc_number] => 20230005991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => ON-PITCH VIAS FOR SEMICONDUCTOR DEVICES AND ASSOCIATED DEVICES AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/929234 [patent_app_country] => US [patent_app_date] => 2022-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17929234 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18097398 [patent_doc_number] => 20220415739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => PACKAGE STRUCTURE AND CIRCUIT LAYER STRUCTURE INCLUDING DUMMY TRACE AND MANUFACTURING METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 17/898299 [patent_app_country] => US [patent_app_date] => 2022-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17898299 [rel_patent_id] =>[rel_patent_doc_number] =>)