Search

John M. Parker

Examiner (ID: 10345, Phone: (571)272-8794 , Office: P/2816 )

Most Active Art Unit
2816
Art Unit(s)
2816, 2823, 2899
Total Applications
1206
Issued Applications
1026
Pending Applications
103
Abandoned Applications
108

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19844177 [patent_doc_number] => 12256593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Display device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/073870 [patent_app_country] => US [patent_app_date] => 2022-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 11362 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18073870 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/073870
Display device and method of manufacturing the same Dec 1, 2022 Issued
Array ( [id] => 18533235 [patent_doc_number] => 20230238311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/058705 [patent_app_country] => US [patent_app_date] => 2022-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7654 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18058705 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/058705
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Nov 22, 2022 Pending
Array ( [id] => 20216143 [patent_doc_number] => 12412797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Hybrid embedded package [patent_app_type] => utility [patent_app_number] => 17/973920 [patent_app_country] => US [patent_app_date] => 2022-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 5 [patent_no_of_words] => 1187 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17973920 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/973920
Hybrid embedded package Oct 25, 2022 Issued
Array ( [id] => 20375342 [patent_doc_number] => 12482786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Hybrid wafer bonding method [patent_app_type] => utility [patent_app_number] => 17/963649 [patent_app_country] => US [patent_app_date] => 2022-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5600 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17963649 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/963649
Hybrid wafer bonding method Oct 10, 2022 Issued
Array ( [id] => 18160423 [patent_doc_number] => 20230027015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => HYBRID WAFER BONDING METHOD AND STRUCTURE THEREOF [patent_app_type] => utility [patent_app_number] => 17/958764 [patent_app_country] => US [patent_app_date] => 2022-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958764 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/958764
Hybrid wafer bonding method and structure thereof Oct 2, 2022 Issued
Array ( [id] => 19859706 [patent_doc_number] => 12262583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Display device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/953463 [patent_app_country] => US [patent_app_date] => 2022-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8842 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17953463 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/953463
Display device and manufacturing method thereof Sep 26, 2022 Issued
Array ( [id] => 18140099 [patent_doc_number] => 20230013938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/947288 [patent_app_country] => US [patent_app_date] => 2022-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17947288 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/947288
INTEGRATED CIRCUIT Sep 18, 2022 Pending
Array ( [id] => 19582501 [patent_doc_number] => 12148628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Semiconductor device and corresponding method [patent_app_type] => utility [patent_app_number] => 17/942843 [patent_app_country] => US [patent_app_date] => 2022-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2616 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17942843 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/942843
Semiconductor device and corresponding method Sep 11, 2022 Issued
Array ( [id] => 18097460 [patent_doc_number] => 20220415801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => INTERCONNECT STRUCTURE AND ELECTRONIC APPARATUS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/902319 [patent_app_country] => US [patent_app_date] => 2022-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17902319 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/902319
Interconnect structure and electronic apparatus including the same Sep 1, 2022 Issued
Array ( [id] => 18113111 [patent_doc_number] => 20230005991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => ON-PITCH VIAS FOR SEMICONDUCTOR DEVICES AND ASSOCIATED DEVICES AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/929234 [patent_app_country] => US [patent_app_date] => 2022-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17929234 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/929234
On-pitch vias for semiconductor devices and associated devices and systems Aug 31, 2022 Issued
Array ( [id] => 18097398 [patent_doc_number] => 20220415739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => PACKAGE STRUCTURE AND CIRCUIT LAYER STRUCTURE INCLUDING DUMMY TRACE AND MANUFACTURING METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 17/898299 [patent_app_country] => US [patent_app_date] => 2022-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17898299 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/898299
Package structure and circuit layer structure including dummy trace and manufacturing method therefor Aug 28, 2022 Issued
Array ( [id] => 18097459 [patent_doc_number] => 20220415800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND APPARATUS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/893349 [patent_app_country] => US [patent_app_date] => 2022-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12447 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893349 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/893349
Semiconductor memory device and apparatus including the same Aug 22, 2022 Issued
Array ( [id] => 19654466 [patent_doc_number] => 12176266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Through-substrate via formation to enlarge electrochemical plating window [patent_app_type] => utility [patent_app_number] => 17/880854 [patent_app_country] => US [patent_app_date] => 2022-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7186 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17880854 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/880854
Through-substrate via formation to enlarge electrochemical plating window Aug 3, 2022 Issued
Array ( [id] => 19627133 [patent_doc_number] => 12165982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Semiconductor package structure and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/879677 [patent_app_country] => US [patent_app_date] => 2022-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7579 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17879677 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/879677
Semiconductor package structure and method for manufacturing the same Aug 1, 2022 Issued
Array ( [id] => 18941139 [patent_doc_number] => 20240036278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => 3D High Bandwidth Memory and Optical Connectivity Stacking [patent_app_type] => utility [patent_app_number] => 17/877041 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3846 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17877041 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/877041
3D High Bandwidth Memory and Optical Connectivity Stacking Jul 28, 2022 Pending
Array ( [id] => 18142671 [patent_doc_number] => 20230016515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => HYBRID CONDUCTIVE STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/875675 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6706 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17875675 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/875675
Hybrid conductive structures Jul 27, 2022 Issued
Array ( [id] => 19597043 [patent_doc_number] => 12154897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Package structures [patent_app_type] => utility [patent_app_number] => 17/874323 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 13648 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874323 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874323
Package structures Jul 26, 2022 Issued
Array ( [id] => 17993230 [patent_doc_number] => 20220359267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/874639 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874639 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874639
Semiconductor device structure and methods of forming the same Jul 26, 2022 Issued
Array ( [id] => 20532268 [patent_doc_number] => 12550721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Inter-wire cavity for low capacitance [patent_app_type] => utility [patent_app_number] => 17/873381 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 45 [patent_no_of_words] => 6158 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873381 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/873381
Inter-wire cavity for low capacitance Jul 25, 2022 Issued
Array ( [id] => 19720343 [patent_doc_number] => 12205886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Hybrid method for forming semiconductor interconnect structure [patent_app_type] => utility [patent_app_number] => 17/873590 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9736 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873590 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/873590
Hybrid method for forming semiconductor interconnect structure Jul 25, 2022 Issued
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