
John M. Parker
Examiner (ID: 11130, Phone: (571)272-8794 , Office: P/2816 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2899, 2823, 2816 |
| Total Applications | 1173 |
| Issued Applications | 1023 |
| Pending Applications | 77 |
| Abandoned Applications | 108 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18223460
[patent_doc_number] => 20230062454
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => Recessed Lid and Ring Designs and Lid Local Peripheral Reinforcement Designs
[patent_app_type] => utility
[patent_app_number] => 17/461207
[patent_app_country] => US
[patent_app_date] => 2021-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3434
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461207
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/461207 | Recessed lid and ring designs and lid local peripheral reinforcement designs | Aug 29, 2021 | Issued |
Array
(
[id] => 18225454
[patent_doc_number] => 20230064448
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => SEMICONDUCTOR STRUCTURE HAVING DIELECTRIC-ON-DIELECTRIC STRUCTURE AND METHOD FOR FORMING THE SEMICONDUCTOR STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/460824
[patent_app_country] => US
[patent_app_date] => 2021-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6199
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460824
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/460824 | Semiconductor structure having dielectric-on-dielectric structure and method for forming the semiconductor structure | Aug 29, 2021 | Issued |
Array
(
[id] => 18228810
[patent_doc_number] => 20230067804
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => Tapered Dielectric Layer for Preventing Electrical Shorting Between Gate and Back Side Via
[patent_app_type] => utility
[patent_app_number] => 17/459342
[patent_app_country] => US
[patent_app_date] => 2021-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11768
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459342
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/459342 | Tapered dielectric layer for preventing electrical shorting between gate and back side via | Aug 26, 2021 | Issued |
Array
(
[id] => 19213677
[patent_doc_number] => 12002749
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-04
[patent_title] => Barrier and air-gap scheme for high performance interconnects
[patent_app_type] => utility
[patent_app_number] => 17/412403
[patent_app_country] => US
[patent_app_date] => 2021-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 20
[patent_no_of_words] => 7502
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412403
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/412403 | Barrier and air-gap scheme for high performance interconnects | Aug 25, 2021 | Issued |
Array
(
[id] => 18857379
[patent_doc_number] => 11854974
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-26
[patent_title] => Advanced node interconnect routing methodology
[patent_app_type] => utility
[patent_app_number] => 17/409025
[patent_app_country] => US
[patent_app_date] => 2021-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 18
[patent_no_of_words] => 16146
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17409025
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/409025 | Advanced node interconnect routing methodology | Aug 22, 2021 | Issued |
Array
(
[id] => 18563178
[patent_doc_number] => 11728433
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-15
[patent_title] => Vertical transistor with self-aligned gate
[patent_app_type] => utility
[patent_app_number] => 17/403294
[patent_app_country] => US
[patent_app_date] => 2021-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 20
[patent_no_of_words] => 8707
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17403294
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/403294 | Vertical transistor with self-aligned gate | Aug 15, 2021 | Issued |
Array
(
[id] => 19487093
[patent_doc_number] => 12106817
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-01
[patent_title] => Method for manufacturing a memory
[patent_app_type] => utility
[patent_app_number] => 17/403570
[patent_app_country] => US
[patent_app_date] => 2021-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 26
[patent_no_of_words] => 9533
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 300
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17403570
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/403570 | Method for manufacturing a memory | Aug 15, 2021 | Issued |
Array
(
[id] => 18184623
[patent_doc_number] => 20230045353
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-09
[patent_title] => MICROELECTRONIC DEVICES INCLUDING ACTIVE CONTACTS AND SUPPORT CONTACTS, AND RELATED ELECTRONIC SYSTEMS AND METHODS
[patent_app_type] => utility
[patent_app_number] => 17/396939
[patent_app_country] => US
[patent_app_date] => 2021-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7418
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396939
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/396939 | Microelectronic devices including active contacts and support contacts, and related electronic systems and methods | Aug 8, 2021 | Issued |
Array
(
[id] => 17262917
[patent_doc_number] => 20210375902
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-02
[patent_title] => Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
[patent_app_type] => utility
[patent_app_number] => 17/396952
[patent_app_country] => US
[patent_app_date] => 2021-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6698
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -31
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396952
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/396952 | Memory arrays and methods used in forming a memory array comprising strings of memory cells | Aug 8, 2021 | Issued |
Array
(
[id] => 19155082
[patent_doc_number] => 11980018
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-05-07
[patent_title] => Semiconductor device and method of fabricating the same
[patent_app_type] => utility
[patent_app_number] => 17/396752
[patent_app_country] => US
[patent_app_date] => 2021-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 6857
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396752
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/396752 | Semiconductor device and method of fabricating the same | Aug 7, 2021 | Issued |
Array
(
[id] => 17232189
[patent_doc_number] => 20210358746
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-18
[patent_title] => WAFER PROCESS, APPARATUS AND METHOD OF MANUFACTURING AN ARTICLE
[patent_app_type] => utility
[patent_app_number] => 17/387243
[patent_app_country] => US
[patent_app_date] => 2021-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3793
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17387243
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/387243 | Wafer process, apparatus and method of manufacturing an article | Jul 27, 2021 | Issued |
Array
(
[id] => 18068138
[patent_doc_number] => 20220399226
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-15
[patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/382379
[patent_app_country] => US
[patent_app_date] => 2021-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4330
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17382379
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/382379 | Semiconductor structure and method for forming the same | Jul 21, 2021 | Issued |
Array
(
[id] => 19314418
[patent_doc_number] => 12040243
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-16
[patent_title] => Module
[patent_app_type] => utility
[patent_app_number] => 17/382815
[patent_app_country] => US
[patent_app_date] => 2021-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 21
[patent_no_of_words] => 4309
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17382815
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/382815 | Module | Jul 21, 2021 | Issued |
Array
(
[id] => 18140317
[patent_doc_number] => 20230014156
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-19
[patent_title] => SEMICONDUCTOR INTERCONNECT STRUCTURE WITH BOTTOM SELF-ALIGNED VIA LANDING
[patent_app_type] => utility
[patent_app_number] => 17/376940
[patent_app_country] => US
[patent_app_date] => 2021-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5472
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17376940
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/376940 | Semiconductor interconnect structure with bottom self-aligned via landing | Jul 14, 2021 | Issued |
Array
(
[id] => 18144846
[patent_doc_number] => 20230018698
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-19
[patent_title] => WRAP AROUND CROSS-COUPLE CONTACT STRUCTURE WITH ENHANCED GATE CONTACT SIZE
[patent_app_type] => utility
[patent_app_number] => 17/375670
[patent_app_country] => US
[patent_app_date] => 2021-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8839
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17375670
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/375670 | Wrap around cross-couple contact structure with enhanced gate contact size | Jul 13, 2021 | Issued |
Array
(
[id] => 19016351
[patent_doc_number] => 11923293
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-05
[patent_title] => Barrier structure on interconnect wire to increase processing window for overlying via
[patent_app_type] => utility
[patent_app_number] => 17/370107
[patent_app_country] => US
[patent_app_date] => 2021-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 18
[patent_no_of_words] => 9796
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370107
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/370107 | Barrier structure on interconnect wire to increase processing window for overlying via | Jul 7, 2021 | Issued |
Array
(
[id] => 17900779
[patent_doc_number] => 20220310441
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-29
[patent_title] => Air Spacer Surrounding Conductive Features and Method Forming Same
[patent_app_type] => utility
[patent_app_number] => 17/369497
[patent_app_country] => US
[patent_app_date] => 2021-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6974
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369497
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/369497 | Air spacer surrounding conductive features and method forming same | Jul 6, 2021 | Issued |
Array
(
[id] => 18481169
[patent_doc_number] => 11694923
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-07-04
[patent_title] => Method for preparing semiconductor device with air spacer
[patent_app_type] => utility
[patent_app_number] => 17/367973
[patent_app_country] => US
[patent_app_date] => 2021-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 7679
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17367973
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/367973 | Method for preparing semiconductor device with air spacer | Jul 5, 2021 | Issued |
Array
(
[id] => 17174376
[patent_doc_number] => 20210328047
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-21
[patent_title] => METHOD OF FORMING SHAPED SOURCE/DRAIN EPITAXIAL LAYERS OF A SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/364623
[patent_app_country] => US
[patent_app_date] => 2021-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5577
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17364623
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/364623 | Method of forming shaped source/drain epitaxial layers of a semiconductor device | Jun 29, 2021 | Issued |
Array
(
[id] => 19176164
[patent_doc_number] => 20240162138
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-16
[patent_title] => METHOD FOR FORMING CONDUCTIVE VIA, CONDUCTIVE VIA AND PASSIVE DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/781013
[patent_app_country] => US
[patent_app_date] => 2021-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 38243
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17781013
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/781013 | METHOD FOR FORMING CONDUCTIVE VIA, CONDUCTIVE VIA AND PASSIVE DEVICE | Jun 24, 2021 | Pending |