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John M. Petruncio

Examiner (ID: 7354)

Most Active Art Unit
1751
Art Unit(s)
1751
Total Applications
394
Issued Applications
318
Pending Applications
23
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20344809 [patent_doc_number] => 12468540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Technologies for prediction-based register renaming [patent_app_type] => utility [patent_app_number] => 18/017792 [patent_app_country] => US [patent_app_date] => 2021-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2450 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18017792 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/017792
Technologies for prediction-based register renaming Jul 22, 2021 Issued
Array ( [id] => 18079492 [patent_doc_number] => 20220405104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => CROSS PLATFORM AND PLATFORM AGNOSTIC ACCELERATOR REMOTING SERVICE [patent_app_type] => utility [patent_app_number] => 17/377893 [patent_app_country] => US [patent_app_date] => 2021-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10099 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377893 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/377893
CROSS PLATFORM AND PLATFORM AGNOSTIC ACCELERATOR REMOTING SERVICE Jul 15, 2021 Pending
Array ( [id] => 18606637 [patent_doc_number] => 11748101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Handling of single-copy-atomic load/store instruction with a memory access request shared by micro-operations [patent_app_type] => utility [patent_app_number] => 17/374149 [patent_app_country] => US [patent_app_date] => 2021-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 14392 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 394 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17374149 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/374149
Handling of single-copy-atomic load/store instruction with a memory access request shared by micro-operations Jul 12, 2021 Issued
Array ( [id] => 18553851 [patent_doc_number] => 20230251863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => MULTI-BIT REGISTER, CHIP, AND COMPUTING APPARATUS [patent_app_type] => utility [patent_app_number] => 18/005281 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4281 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18005281 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/005281
MULTI-BIT REGISTER, CHIP, AND COMPUTING APPARATUS Jul 6, 2021 Pending
Array ( [id] => 17261038 [patent_doc_number] => 20210374023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => FLEXIBLE INTERFACE [patent_app_type] => utility [patent_app_number] => 17/368450 [patent_app_country] => US [patent_app_date] => 2021-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17368450 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/368450
FLEXIBLE INTERFACE Jul 5, 2021 Pending
Array ( [id] => 18095513 [patent_doc_number] => 20220413854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => 64-BIT TWO-DIMENSIONAL BLOCK LOAD WITH TRANSPOSE [patent_app_type] => utility [patent_app_number] => 17/358859 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 47188 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17358859 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/358859
64-BIT TWO-DIMENSIONAL BLOCK LOAD WITH TRANSPOSE Jun 24, 2021 Pending
Array ( [id] => 20647286 [patent_doc_number] => 12602229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-14 [patent_title] => Neural network accelerator for operating a consumer pipeline stage using a start flag set by a producer pipeline stage [patent_app_type] => utility [patent_app_number] => 17/351408 [patent_app_country] => US [patent_app_date] => 2021-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 22675 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17351408 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/351408
Neural network accelerator for operating a consumer pipeline stage using a start flag set by a producer pipeline stage Jun 17, 2021 Issued
Array ( [id] => 17230660 [patent_doc_number] => 20210357217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => SYSTEMS AND METHODS FOR EXECUTING A FUSED MULTIPLY-ADD INSTRUCTION FOR COMPLEX NUMBERS [patent_app_type] => utility [patent_app_number] => 17/335942 [patent_app_country] => US [patent_app_date] => 2021-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17335942 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/335942
SYSTEMS AND METHODS FOR EXECUTING A FUSED MULTIPLY-ADD INSTRUCTION FOR COMPLEX NUMBERS May 31, 2021 Abandoned
Array ( [id] => 17613801 [patent_doc_number] => 20220156081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => PROCESSING-IN-MEMORY AND METHOD OF OUTPUTTING INSTRUCTION USING PROCESSING-IN-MEMORY [patent_app_type] => utility [patent_app_number] => 17/323171 [patent_app_country] => US [patent_app_date] => 2021-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17323171 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/323171
Processor-in-memory storing a lookup table for providing an instruction in response to an API call instruction May 17, 2021 Issued
Array ( [id] => 19581693 [patent_doc_number] => 12147811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Warp scheduling method for adjusting number of schedulable warps based on load/store unit stall cycle proportion [patent_app_type] => utility [patent_app_number] => 17/227422 [patent_app_country] => US [patent_app_date] => 2021-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6877 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17227422 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/227422
Warp scheduling method for adjusting number of schedulable warps based on load/store unit stall cycle proportion Apr 11, 2021 Issued
Array ( [id] => 17899228 [patent_doc_number] => 20220308890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => MULTI-PROCESSING UNIT INTERCONNECTED ACCELERATOR SYSTEMS AND CONFIGURATION TECHNIQUES [patent_app_type] => utility [patent_app_number] => 17/216189 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4364 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17216189 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/216189
MULTI-PROCESSING UNIT INTERCONNECTED ACCELERATOR SYSTEMS AND CONFIGURATION TECHNIQUES Mar 28, 2021 Pending
Array ( [id] => 18839386 [patent_doc_number] => 11847460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Adaptive load coalescing for spatially proximate load requests based on predicted load request coalescence based on handling of previous load requests [patent_app_type] => utility [patent_app_number] => 17/211062 [patent_app_country] => US [patent_app_date] => 2021-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8303 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17211062 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/211062
Adaptive load coalescing for spatially proximate load requests based on predicted load request coalescence based on handling of previous load requests Mar 23, 2021 Issued
Array ( [id] => 18677832 [patent_doc_number] => 20230315479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => METHOD AND SYSTEM FOR SUPPORTING THROUGHPUT-ORIENTED COMPUTING [patent_app_type] => utility [patent_app_number] => 18/023755 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7966 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18023755 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/023755
METHOD AND SYSTEM FOR SUPPORTING THROUGHPUT-ORIENTED COMPUTING Feb 24, 2021 Abandoned
Array ( [id] => 17009317 [patent_doc_number] => 20210240478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => SYSTEM AND METHOD FOR GENERATING DATA-FLOW ANALYSIS PIPELINES [patent_app_type] => utility [patent_app_number] => 17/167750 [patent_app_country] => US [patent_app_date] => 2021-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8534 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17167750 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/167750
SYSTEM AND METHOD FOR GENERATING DATA-FLOW ANALYSIS PIPELINES Feb 3, 2021 Abandoned
Array ( [id] => 17446993 [patent_doc_number] => 20220067498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => APPARATUS AND METHOD WITH NEURAL NETWORK OPERATION [patent_app_type] => utility [patent_app_number] => 17/162326 [patent_app_country] => US [patent_app_date] => 2021-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17162326 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/162326
APPARATUS AND METHOD WITH NEURAL NETWORK OPERATION Jan 28, 2021 Pending
Array ( [id] => 16826578 [patent_doc_number] => 20210141871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => METHOD AND SYSTEM OF VERIFYING PROPER EXECUTION OF A SECURE MODE ENTRY SEQUENCE [patent_app_type] => utility [patent_app_number] => 17/156717 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4610 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17156717 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/156717
METHOD AND SYSTEM OF VERIFYING PROPER EXECUTION OF A SECURE MODE ENTRY SEQUENCE Jan 24, 2021 Abandoned
Array ( [id] => 17316983 [patent_doc_number] => 20210406032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => COMPLEX COMPUTING DEVICE, COMPLEX COMPUTING METHOD, ARTIFICIAL INTELLIGENCE CHIP AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 17/149476 [patent_app_country] => US [patent_app_date] => 2021-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5272 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17149476 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/149476
Input and output interfaces for transmitting complex computing information between AI processors and computing components of a special function unit Jan 13, 2021 Issued
Array ( [id] => 16849580 [patent_doc_number] => 20210150325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => DATA PROCESSING METHOD AND APPARATUS, AND RELATED PRODUCT [patent_app_type] => utility [patent_app_number] => 17/137245 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11550 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137245 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137245
DATA PROCESSING METHOD AND APPARATUS, AND RELATED PRODUCT Dec 28, 2020 Pending
Array ( [id] => 17706787 [patent_doc_number] => 20220206793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => METHODS, SYSTEMS, AND APPARATUSES FOR A SCALABLE RESERVATION STATION IMPLEMENTING A SINGLE UNIFIED SPECULATION STATE PROPAGATION AND EXECUTION WAKEUP MATRIX CIRCUIT IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/134154 [patent_app_country] => US [patent_app_date] => 2020-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21486 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134154 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134154
METHODS, SYSTEMS, AND APPARATUSES FOR A SCALABLE RESERVATION STATION IMPLEMENTING A SINGLE UNIFIED SPECULATION STATE PROPAGATION AND EXECUTION WAKEUP MATRIX CIRCUIT IN A PROCESSOR Dec 23, 2020 Abandoned
Array ( [id] => 17507410 [patent_doc_number] => 20220100513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS FOR LOADING DATA AND PADDING INTO A TILE OF A MATRIX OPERATIONS ACCELERATOR [patent_app_type] => utility [patent_app_number] => 17/134085 [patent_app_country] => US [patent_app_date] => 2020-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134085 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134085
APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS FOR LOADING DATA AND PADDING INTO A TILE OF A MATRIX OPERATIONS ACCELERATOR Dec 23, 2020 Abandoned
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