Search

John M. Sollecito

Examiner (ID: 15396)

Most Active Art Unit
3404
Art Unit(s)
3404, 3744
Total Applications
998
Issued Applications
895
Pending Applications
31
Abandoned Applications
72

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8189634 [patent_doc_number] => 20120117614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'SYSTEM AND METHOD FOR HIGH PERFORMANCE SECURE ACCESS TO A TRUSTED PLATFORM MODULE ON A HARDWARE VIRTUALIZATION PLATFORM' [patent_app_type] => utility [patent_app_number] => 13/305902 [patent_app_country] => US [patent_app_date] => 2011-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7835 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20120117614.pdf [firstpage_image] =>[orig_patent_app_number] => 13305902 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/305902
System and method for high performance secure access to a trusted platform module on a hardware virtualization platform Nov 28, 2011 Issued
Array ( [id] => 7780567 [patent_doc_number] => 20120042123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-16 [patent_title] => 'INTELLIGENT CACHE MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 13/278541 [patent_app_country] => US [patent_app_date] => 2011-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4443 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20120042123.pdf [firstpage_image] =>[orig_patent_app_number] => 13278541 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/278541
INTELLIGENT CACHE MANAGEMENT Oct 20, 2011 Abandoned
Array ( [id] => 10183888 [patent_doc_number] => 09213567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-15 [patent_title] => 'System and method for controlling the input/output of a virtualized network' [patent_app_type] => utility [patent_app_number] => 13/247578 [patent_app_country] => US [patent_app_date] => 2011-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6217 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13247578 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/247578
System and method for controlling the input/output of a virtualized network Sep 27, 2011 Issued
Array ( [id] => 10189427 [patent_doc_number] => 09218852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-22 [patent_title] => 'Smart bridge for memory core' [patent_app_type] => utility [patent_app_number] => 13/247592 [patent_app_country] => US [patent_app_date] => 2011-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 13868 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13247592 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/247592
Smart bridge for memory core Sep 27, 2011 Issued
Array ( [id] => 8588528 [patent_doc_number] => 20130007349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'SMART BRIDGE FOR MEMORY CORE' [patent_app_type] => utility [patent_app_number] => 13/247532 [patent_app_country] => US [patent_app_date] => 2011-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13863 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13247532 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/247532
Smart bridge for memory core Sep 27, 2011 Issued
Array ( [id] => 10184037 [patent_doc_number] => 09213717 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-12-15 [patent_title] => 'Managing concurrent I/OS in file systems' [patent_app_type] => utility [patent_app_number] => 13/247753 [patent_app_country] => US [patent_app_date] => 2011-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13247753 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/247753
Managing concurrent I/OS in file systems Sep 27, 2011 Issued
Array ( [id] => 8735145 [patent_doc_number] => 20130080714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'I/O MEMORY TRANSLATION UNIT WITH SUPPORT FOR LEGACY DEVICES' [patent_app_type] => utility [patent_app_number] => 13/247457 [patent_app_country] => US [patent_app_date] => 2011-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8108 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13247457 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/247457
I/O MEMORY TRANSLATION UNIT WITH SUPPORT FOR LEGACY DEVICES Sep 27, 2011 Abandoned
Array ( [id] => 8650559 [patent_doc_number] => 20130036289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-07 [patent_title] => 'STORAGE SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/640130 [patent_app_country] => US [patent_app_date] => 2011-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 16330 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13640130 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/640130
System and method for deduplication of distributed data Sep 20, 2011 Issued
Array ( [id] => 8709984 [patent_doc_number] => 20130067273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-14 [patent_title] => 'Optimizing and Enhancing Performance for Parity Based Storage' [patent_app_type] => utility [patent_app_number] => 13/230248 [patent_app_country] => US [patent_app_date] => 2011-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7836 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13230248 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/230248
Optimizing and enhancing performance for parity based storage Sep 11, 2011 Issued
Array ( [id] => 11232775 [patent_doc_number] => 09460004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-04 [patent_title] => 'Memory erasing method, memory controller, and memory storage apparatus' [patent_app_type] => utility [patent_app_number] => 13/213107 [patent_app_country] => US [patent_app_date] => 2011-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 7872 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13213107 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/213107
Memory erasing method, memory controller, and memory storage apparatus Aug 18, 2011 Issued
Array ( [id] => 11801457 [patent_doc_number] => 09542334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Memory management unit TAG memory with CAM evaluate signal' [patent_app_type] => utility [patent_app_number] => 13/213831 [patent_app_country] => US [patent_app_date] => 2011-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 13032 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13213831 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/213831
Memory management unit TAG memory with CAM evaluate signal Aug 18, 2011 Issued
Array ( [id] => 8672390 [patent_doc_number] => 20130046928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'Memory Management Unit Tag Memory' [patent_app_type] => utility [patent_app_number] => 13/213900 [patent_app_country] => US [patent_app_date] => 2011-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11830 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13213900 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/213900
Memory management unit tag memory Aug 18, 2011 Issued
Array ( [id] => 11193374 [patent_doc_number] => 09424190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-23 [patent_title] => 'Data processing system operable in single and multi-thread modes and having multiple caches and method of operation' [patent_app_type] => utility [patent_app_number] => 13/213387 [patent_app_country] => US [patent_app_date] => 2011-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 18291 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13213387 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/213387
Data processing system operable in single and multi-thread modes and having multiple caches and method of operation Aug 18, 2011 Issued
Array ( [id] => 8672413 [patent_doc_number] => 20130046951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'PARALLEL DYNAMIC MEMORY ALLOCATION USING A NESTED HIERARCHICAL HEAP' [patent_app_type] => utility [patent_app_number] => 13/214101 [patent_app_country] => US [patent_app_date] => 2011-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12179 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13214101 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/214101
Parallel dynamic memory allocation using a nested hierarchical heap Aug 18, 2011 Issued
Array ( [id] => 7785765 [patent_doc_number] => 20120047321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-23 [patent_title] => 'Address Scheduling Methods For Non-Volatile Memory Devices With Three-Dimensional Memory Cell Arrays' [patent_app_type] => utility [patent_app_number] => 13/213806 [patent_app_country] => US [patent_app_date] => 2011-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7697 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20120047321.pdf [firstpage_image] =>[orig_patent_app_number] => 13213806 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/213806
Address Scheduling Methods For Non-Volatile Memory Devices With Three-Dimensional Memory Cell Arrays Aug 18, 2011 Abandoned
Array ( [id] => 9275931 [patent_doc_number] => 08639878 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-01-28 [patent_title] => 'Providing redundancy in a storage system' [patent_app_type] => utility [patent_app_number] => 13/204070 [patent_app_country] => US [patent_app_date] => 2011-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 10703 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13204070 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/204070
Providing redundancy in a storage system Aug 4, 2011 Issued
Array ( [id] => 9378890 [patent_doc_number] => 08683172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-25 [patent_title] => 'Method and apparatus for management between virtualized machines and virtualized storage systems' [patent_app_type] => utility [patent_app_number] => 13/080741 [patent_app_country] => US [patent_app_date] => 2011-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 32 [patent_no_of_words] => 17983 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13080741 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/080741
Method and apparatus for management between virtualized machines and virtualized storage systems Apr 5, 2011 Issued
Array ( [id] => 8395540 [patent_doc_number] => 20120233380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'SYSTEMS, DEVICES, MEMORY CONTROLLERS, AND METHODS FOR CONTROLLING MEMORY' [patent_app_type] => utility [patent_app_number] => 13/046439 [patent_app_country] => US [patent_app_date] => 2011-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6696 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13046439 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/046439
Systems, devices, memory controllers, and methods for controlling memory Mar 10, 2011 Issued
Array ( [id] => 5976258 [patent_doc_number] => 20110153919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'DEVICE, SYSTEM, AND METHOD FOR REDUCING PROGRAM/READ DISTURB IN FLASH ARRAYS' [patent_app_type] => utility [patent_app_number] => 12/969500 [patent_app_country] => US [patent_app_date] => 2010-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6811 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20110153919.pdf [firstpage_image] =>[orig_patent_app_number] => 12969500 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/969500
Device, system, and method for reducing program/read disturb in flash arrays Dec 14, 2010 Issued
Array ( [id] => 8254784 [patent_doc_number] => 20120159109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'METHOD AND APPARATUS FOR IMPROVING NON-UNIFORM MEMORY ACCESS' [patent_app_type] => utility [patent_app_number] => 12/969520 [patent_app_country] => US [patent_app_date] => 2010-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6831 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20120159109.pdf [firstpage_image] =>[orig_patent_app_number] => 12969520 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/969520
Method and apparatus for improving non-uniform memory access Dec 14, 2010 Issued
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