Search

John M. Sollecito

Examiner (ID: 12504)

Most Active Art Unit
3404
Art Unit(s)
3404, 3744
Total Applications
998
Issued Applications
895
Pending Applications
31
Abandoned Applications
72

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3796131 [patent_doc_number] => 05758101 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Method and apparatus for connecting and disconnecting peripheral devices to a powered bus' [patent_app_type] => 1 [patent_app_number] => 8/502575 [patent_app_country] => US [patent_app_date] => 1995-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5169 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/758/05758101.pdf [firstpage_image] =>[orig_patent_app_number] => 502575 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/502575
Method and apparatus for connecting and disconnecting peripheral devices to a powered bus Jul 13, 1995 Issued
Array ( [id] => 3601553 [patent_doc_number] => 05551032 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-27 [patent_title] => 'Method for file transfer' [patent_app_type] => 1 [patent_app_number] => 8/497244 [patent_app_country] => US [patent_app_date] => 1995-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1876 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/551/05551032.pdf [firstpage_image] =>[orig_patent_app_number] => 497244 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/497244
Method for file transfer Jun 29, 1995 Issued
Array ( [id] => 3599792 [patent_doc_number] => 05553240 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-03 [patent_title] => 'Determining a winner of a race in a data processing system' [patent_app_type] => 1 [patent_app_number] => 8/494868 [patent_app_country] => US [patent_app_date] => 1995-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4525 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/553/05553240.pdf [firstpage_image] =>[orig_patent_app_number] => 494868 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/494868
Determining a winner of a race in a data processing system Jun 25, 1995 Issued
Array ( [id] => 3662884 [patent_doc_number] => 05684998 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Apparatus and method for suspending and resuming software applications on a computer' [patent_app_type] => 1 [patent_app_number] => 8/489214 [patent_app_country] => US [patent_app_date] => 1995-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 29 [patent_no_of_words] => 9358 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/684/05684998.pdf [firstpage_image] =>[orig_patent_app_number] => 489214 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/489214
Apparatus and method for suspending and resuming software applications on a computer Jun 11, 1995 Issued
Array ( [id] => 3672851 [patent_doc_number] => 05649129 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'GPIB system including controller and analyzer' [patent_app_type] => 1 [patent_app_number] => 8/475067 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 12515 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649129.pdf [firstpage_image] =>[orig_patent_app_number] => 475067 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/475067
GPIB system including controller and analyzer Jun 6, 1995 Issued
Array ( [id] => 3784299 [patent_doc_number] => 05734843 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Reverse data channel as a bandwidth modulator' [patent_app_type] => 1 [patent_app_number] => 8/476872 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3217 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/734/05734843.pdf [firstpage_image] =>[orig_patent_app_number] => 476872 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/476872
Reverse data channel as a bandwidth modulator Jun 6, 1995 Issued
Array ( [id] => 3669538 [patent_doc_number] => 05659688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Technique and circuit for providing two or more processors with time multiplexed access to a shared system resource' [patent_app_type] => 1 [patent_app_number] => 8/487711 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2414 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659688.pdf [firstpage_image] =>[orig_patent_app_number] => 487711 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/487711
Technique and circuit for providing two or more processors with time multiplexed access to a shared system resource Jun 6, 1995 Issued
Array ( [id] => 3700032 [patent_doc_number] => 05696913 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Unique processor identifier in a multi-processing system having plural memories with a unified address space corresponding to each processor' [patent_app_type] => 1 [patent_app_number] => 8/472827 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 64 [patent_no_of_words] => 37744 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696913.pdf [firstpage_image] =>[orig_patent_app_number] => 472827 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/472827
Unique processor identifier in a multi-processing system having plural memories with a unified address space corresponding to each processor Jun 6, 1995 Issued
Array ( [id] => 3566824 [patent_doc_number] => 05574921 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-12 [patent_title] => 'Method and apparatus for reducing bus noise and power consumption' [patent_app_type] => 1 [patent_app_number] => 8/468484 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4606 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/574/05574921.pdf [firstpage_image] =>[orig_patent_app_number] => 468484 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/468484
Method and apparatus for reducing bus noise and power consumption Jun 5, 1995 Issued
Array ( [id] => 3625417 [patent_doc_number] => 05566305 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-15 [patent_title] => 'Duplicated logic and interconnection system for arbitration among multiple information processors' [patent_app_type] => 1 [patent_app_number] => 8/462673 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9521 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/566/05566305.pdf [firstpage_image] =>[orig_patent_app_number] => 462673 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/462673
Duplicated logic and interconnection system for arbitration among multiple information processors Jun 4, 1995 Issued
Array ( [id] => 3604293 [patent_doc_number] => 05586331 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Duplicated logic and interconnection system for arbitration among multiple information processors' [patent_app_type] => 1 [patent_app_number] => 8/459456 [patent_app_country] => US [patent_app_date] => 1995-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9519 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586331.pdf [firstpage_image] =>[orig_patent_app_number] => 459456 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/459456
Duplicated logic and interconnection system for arbitration among multiple information processors Jun 1, 1995 Issued
Array ( [id] => 3544101 [patent_doc_number] => 05583997 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'System for extending network resources to remote networks' [patent_app_type] => 1 [patent_app_number] => 8/456390 [patent_app_country] => US [patent_app_date] => 1995-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5459 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/583/05583997.pdf [firstpage_image] =>[orig_patent_app_number] => 456390 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/456390
System for extending network resources to remote networks May 31, 1995 Issued
08/450375 REDUCING POWER USAGE IN A PERSONAL COMPUTER May 24, 1995 Abandoned
Array ( [id] => 3717124 [patent_doc_number] => 05675810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Reducing power usage in a personal computer' [patent_app_type] => 1 [patent_app_number] => 8/450361 [patent_app_country] => US [patent_app_date] => 1995-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2529 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675810.pdf [firstpage_image] =>[orig_patent_app_number] => 450361 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/450361
Reducing power usage in a personal computer May 24, 1995 Issued
Array ( [id] => 3530213 [patent_doc_number] => 05577214 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-19 [patent_title] => 'Programmable hold delay' [patent_app_type] => 1 [patent_app_number] => 8/448050 [patent_app_country] => US [patent_app_date] => 1995-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 23428 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/577/05577214.pdf [firstpage_image] =>[orig_patent_app_number] => 448050 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/448050
Programmable hold delay May 22, 1995 Issued
Array ( [id] => 3775537 [patent_doc_number] => 05742762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-21 [patent_title] => 'Network management gateway' [patent_app_type] => 1 [patent_app_number] => 8/444483 [patent_app_country] => US [patent_app_date] => 1995-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5291 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/742/05742762.pdf [firstpage_image] =>[orig_patent_app_number] => 444483 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/444483
Network management gateway May 18, 1995 Issued
Array ( [id] => 3734079 [patent_doc_number] => 05682483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Apparatus and method for integrating bus master ownership of local bus load by plural data transceivers' [patent_app_type] => 1 [patent_app_number] => 8/442318 [patent_app_country] => US [patent_app_date] => 1995-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7539 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682483.pdf [firstpage_image] =>[orig_patent_app_number] => 442318 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/442318
Apparatus and method for integrating bus master ownership of local bus load by plural data transceivers May 15, 1995 Issued
Array ( [id] => 3893188 [patent_doc_number] => 05729684 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Method and apparatus for heterogeneous multimedia conferencing using multipoint references' [patent_app_type] => 1 [patent_app_number] => 8/442350 [patent_app_country] => US [patent_app_date] => 1995-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3027 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/729/05729684.pdf [firstpage_image] =>[orig_patent_app_number] => 442350 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/442350
Method and apparatus for heterogeneous multimedia conferencing using multipoint references May 15, 1995 Issued
08/437174 DELAYED INTERRUPTS WITH A FIFO IN AN IMPROVED INPUT/OUTPUT ARCHITECTURE May 7, 1995 Abandoned
Array ( [id] => 3708154 [patent_doc_number] => 05596755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Mechanism for using common code to handle hardware interrupts in multiple processor modes' [patent_app_type] => 1 [patent_app_number] => 8/436085 [patent_app_country] => US [patent_app_date] => 1995-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 5844 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/596/05596755.pdf [firstpage_image] =>[orig_patent_app_number] => 436085 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/436085
Mechanism for using common code to handle hardware interrupts in multiple processor modes May 7, 1995 Issued
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