
John M. Sollecito
Examiner (ID: 12504)
| Most Active Art Unit | 3404 |
| Art Unit(s) | 3404, 3744 |
| Total Applications | 998 |
| Issued Applications | 895 |
| Pending Applications | 31 |
| Abandoned Applications | 72 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3796131
[patent_doc_number] => 05758101
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-26
[patent_title] => 'Method and apparatus for connecting and disconnecting peripheral devices to a powered bus'
[patent_app_type] => 1
[patent_app_number] => 8/502575
[patent_app_country] => US
[patent_app_date] => 1995-07-14
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[patent_no_of_words] => 5169
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[pdf_file] => patents/05/758/05758101.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/502575 | Method and apparatus for connecting and disconnecting peripheral devices to a powered bus | Jul 13, 1995 | Issued |
Array
(
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[patent_doc_number] => 05551032
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-27
[patent_title] => 'Method for file transfer'
[patent_app_type] => 1
[patent_app_number] => 8/497244
[patent_app_country] => US
[patent_app_date] => 1995-06-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/497244 | Method for file transfer | Jun 29, 1995 | Issued |
Array
(
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[patent_doc_number] => 05553240
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[patent_kind] => NA
[patent_issue_date] => 1996-09-03
[patent_title] => 'Determining a winner of a race in a data processing system'
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[patent_app_number] => 8/494868
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[patent_app_date] => 1995-06-26
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Array
(
[id] => 3662884
[patent_doc_number] => 05684998
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[patent_kind] => NA
[patent_issue_date] => 1997-11-04
[patent_title] => 'Apparatus and method for suspending and resuming software applications on a computer'
[patent_app_type] => 1
[patent_app_number] => 8/489214
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[patent_app_date] => 1995-06-12
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[patent_drawing_sheets_cnt] => 27
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/489214 | Apparatus and method for suspending and resuming software applications on a computer | Jun 11, 1995 | Issued |
Array
(
[id] => 3672851
[patent_doc_number] => 05649129
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[patent_kind] => NA
[patent_issue_date] => 1997-07-15
[patent_title] => 'GPIB system including controller and analyzer'
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[patent_app_country] => US
[patent_app_date] => 1995-06-07
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[firstpage_image] =>[orig_patent_app_number] => 475067
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Array
(
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[patent_title] => 'Reverse data channel as a bandwidth modulator'
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[pdf_file] => patents/05/734/05734843.pdf
[firstpage_image] =>[orig_patent_app_number] => 476872
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/476872 | Reverse data channel as a bandwidth modulator | Jun 6, 1995 | Issued |
Array
(
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[patent_doc_number] => 05659688
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[patent_title] => 'Technique and circuit for providing two or more processors with time multiplexed access to a shared system resource'
[patent_app_type] => 1
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[pdf_file] => patents/05/659/05659688.pdf
[firstpage_image] =>[orig_patent_app_number] => 487711
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/487711 | Technique and circuit for providing two or more processors with time multiplexed access to a shared system resource | Jun 6, 1995 | Issued |
Array
(
[id] => 3700032
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[patent_kind] => NA
[patent_issue_date] => 1997-12-09
[patent_title] => 'Unique processor identifier in a multi-processing system having plural memories with a unified address space corresponding to each processor'
[patent_app_type] => 1
[patent_app_number] => 8/472827
[patent_app_country] => US
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[pdf_file] => patents/05/696/05696913.pdf
[firstpage_image] =>[orig_patent_app_number] => 472827
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/472827 | Unique processor identifier in a multi-processing system having plural memories with a unified address space corresponding to each processor | Jun 6, 1995 | Issued |
Array
(
[id] => 3566824
[patent_doc_number] => 05574921
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-12
[patent_title] => 'Method and apparatus for reducing bus noise and power consumption'
[patent_app_type] => 1
[patent_app_number] => 8/468484
[patent_app_country] => US
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[pdf_file] => patents/05/574/05574921.pdf
[firstpage_image] =>[orig_patent_app_number] => 468484
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/468484 | Method and apparatus for reducing bus noise and power consumption | Jun 5, 1995 | Issued |
Array
(
[id] => 3625417
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[patent_issue_date] => 1996-10-15
[patent_title] => 'Duplicated logic and interconnection system for arbitration among multiple information processors'
[patent_app_type] => 1
[patent_app_number] => 8/462673
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[patent_app_date] => 1995-06-05
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Array
(
[id] => 3604293
[patent_doc_number] => 05586331
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[patent_title] => 'Duplicated logic and interconnection system for arbitration among multiple information processors'
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[firstpage_image] =>[orig_patent_app_number] => 459456
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Array
(
[id] => 3544101
[patent_doc_number] => 05583997
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[patent_kind] => NA
[patent_issue_date] => 1996-12-10
[patent_title] => 'System for extending network resources to remote networks'
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[firstpage_image] =>[orig_patent_app_number] => 456390
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/456390 | System for extending network resources to remote networks | May 31, 1995 | Issued |
| 08/450375 | REDUCING POWER USAGE IN A PERSONAL COMPUTER | May 24, 1995 | Abandoned |
Array
(
[id] => 3717124
[patent_doc_number] => 05675810
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[patent_issue_date] => 1997-10-07
[patent_title] => 'Reducing power usage in a personal computer'
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[firstpage_image] =>[orig_patent_app_number] => 450361
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Array
(
[id] => 3530213
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Array
(
[id] => 3775537
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Array
(
[id] => 3734079
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Array
(
[id] => 3893188
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| 08/437174 | DELAYED INTERRUPTS WITH A FIFO IN AN IMPROVED INPUT/OUTPUT ARCHITECTURE | May 7, 1995 | Abandoned |
Array
(
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