Search

John M. Winter

Examiner (ID: 13780, Phone: (571)272-6713 , Office: P/3685 )

Most Active Art Unit
3685
Art Unit(s)
3685, 3621
Total Applications
697
Issued Applications
256
Pending Applications
52
Abandoned Applications
389

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14982679 [patent_doc_number] => 10445251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Wear leveling in non-volatile memories [patent_app_type] => utility [patent_app_number] => 15/627135 [patent_app_country] => US [patent_app_date] => 2017-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 32 [patent_no_of_words] => 16516 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15627135 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/627135
Wear leveling in non-volatile memories Jun 18, 2017 Issued
Array ( [id] => 11989413 [patent_doc_number] => 20170293568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'WEAR LEVELING IN NON-VOLATILE MEMORIES' [patent_app_type] => utility [patent_app_number] => 15/627091 [patent_app_country] => US [patent_app_date] => 2017-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 16961 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15627091 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/627091
Wear leveling in non-volatile memories Jun 18, 2017 Issued
Array ( [id] => 11989400 [patent_doc_number] => 20170293555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'DETERMINING CONTROL STATES FOR ADDRESS MAPPING IN NON-VOLATILE MEMORIES' [patent_app_type] => utility [patent_app_number] => 15/627042 [patent_app_country] => US [patent_app_date] => 2017-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 17371 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15627042 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/627042
Determining control states for address mapping in non-volatile memories Jun 18, 2017 Issued
Array ( [id] => 13627201 [patent_doc_number] => 20180365152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => CACHE STRUCTURE USING A LOGICAL DIRECTORY [patent_app_type] => utility [patent_app_number] => 15/625223 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10355 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15625223 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/625223
Cache structure using a logical directory Jun 15, 2017 Issued
Array ( [id] => 15701171 [patent_doc_number] => 10606762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Sharing virtual and real translations in a virtual cache [patent_app_type] => utility [patent_app_number] => 15/625336 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13451 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15625336 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/625336
Sharing virtual and real translations in a virtual cache Jun 15, 2017 Issued
Array ( [id] => 14601265 [patent_doc_number] => 10353825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => Suspending translation look-aside buffer purge execution in a multi-processor environment [patent_app_type] => utility [patent_app_number] => 15/625444 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7499 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15625444 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/625444
Suspending translation look-aside buffer purge execution in a multi-processor environment Jun 15, 2017 Issued
Array ( [id] => 15313275 [patent_doc_number] => 10521342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Memory address decoding prioritization [patent_app_type] => utility [patent_app_number] => 15/616206 [patent_app_country] => US [patent_app_date] => 2017-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 12758 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15616206 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/616206
Memory address decoding prioritization Jun 6, 2017 Issued
Array ( [id] => 13269097 [patent_doc_number] => 10146633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Data recovery from multiple data backup technologies [patent_app_type] => utility [patent_app_number] => 15/582335 [patent_app_country] => US [patent_app_date] => 2017-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4466 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15582335 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/582335
Data recovery from multiple data backup technologies Apr 27, 2017 Issued
Array ( [id] => 15579439 [patent_doc_number] => 10580110 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Hardware structure to track page reuse [patent_app_type] => utility [patent_app_number] => 15/496637 [patent_app_country] => US [patent_app_date] => 2017-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4935 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15496637 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/496637
Hardware structure to track page reuse Apr 24, 2017 Issued
Array ( [id] => 14523587 [patent_doc_number] => 10339055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Cache system with multiple cache unit states [patent_app_type] => utility [patent_app_number] => 15/492736 [patent_app_country] => US [patent_app_date] => 2017-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15492736 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/492736
Cache system with multiple cache unit states Apr 19, 2017 Issued
Array ( [id] => 11708972 [patent_doc_number] => 20170177470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'ACCESS NETWORK FOR ADDRESS MAPPING IN NON-VOLATILE MEMORIES' [patent_app_type] => utility [patent_app_number] => 15/449612 [patent_app_country] => US [patent_app_date] => 2017-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 12495 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15449612 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/449612
Access network for address mapping in non-volatile memories Mar 2, 2017 Issued
Array ( [id] => 11651598 [patent_doc_number] => 20170147498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'SYSTEM AND METHOD FOR UPDATING AN INSTRUCTION CACHE FOLLOWING A BRANCH INSTRUCTION IN A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/423681 [patent_app_country] => US [patent_app_date] => 2017-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9458 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15423681 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/423681
SYSTEM AND METHOD FOR UPDATING AN INSTRUCTION CACHE FOLLOWING A BRANCH INSTRUCTION IN A SEMICONDUCTOR DEVICE Feb 2, 2017 Abandoned
Array ( [id] => 13332485 [patent_doc_number] => 20180217780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => APPARATUS, METHOD, AND PROGRAM PRODUCT FOR TAPE POSITIONING [patent_app_type] => utility [patent_app_number] => 15/423394 [patent_app_country] => US [patent_app_date] => 2017-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6233 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15423394 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/423394
Apparatus, method, and program product for tape positioning Feb 1, 2017 Issued
Array ( [id] => 16895090 [patent_doc_number] => 11036644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Data processing systems [patent_app_type] => utility [patent_app_number] => 15/423497 [patent_app_country] => US [patent_app_date] => 2017-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 16011 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15423497 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/423497
Data processing systems Feb 1, 2017 Issued
Array ( [id] => 15012933 [patent_doc_number] => 10452612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Efficient data caching management in scalable multi-stage data processing systems [patent_app_type] => utility [patent_app_number] => 15/423384 [patent_app_country] => US [patent_app_date] => 2017-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 11639 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15423384 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/423384
Efficient data caching management in scalable multi-stage data processing systems Feb 1, 2017 Issued
Array ( [id] => 12985843 [patent_doc_number] => 20170344307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => BLOCK CLEANUP: PAGE RECLAMATION PROCESS TO REDUCE GARBAGE COLLECTION OVERHEAD IN DUAL-PROGRAMMABLE NAND FLASH DEVICES [patent_app_type] => utility [patent_app_number] => 15/405227 [patent_app_country] => US [patent_app_date] => 2017-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15405227 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/405227
Block cleanup: page reclamation process to reduce garbage collection overhead in dual-programmable NAND flash devices Jan 11, 2017 Issued
Array ( [id] => 12646683 [patent_doc_number] => 20180107392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => MEMORY MANAGEMENT SYSTEM AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/297745 [patent_app_country] => US [patent_app_date] => 2016-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15297745 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/297745
MEMORY MANAGEMENT SYSTEM AND METHOD THEREOF Oct 18, 2016 Abandoned
Array ( [id] => 12221583 [patent_doc_number] => 20180059943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'Media Controller and Method for Management of CPU-Attached Non-Volatile Memory' [patent_app_type] => utility [patent_app_number] => 15/297953 [patent_app_country] => US [patent_app_date] => 2016-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13736 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15297953 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/297953
Media Controller and Method for Management of CPU-Attached Non-Volatile Memory Oct 18, 2016 Abandoned
Array ( [id] => 15609109 [patent_doc_number] => 10585614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Subtier-level data assignment in a tiered storage system [patent_app_type] => utility [patent_app_number] => 15/297750 [patent_app_country] => US [patent_app_date] => 2016-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8115 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15297750 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/297750
Subtier-level data assignment in a tiered storage system Oct 18, 2016 Issued
Array ( [id] => 12234800 [patent_doc_number] => 20180067663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'MANAGING UNEQUAL NETWORK SHARED DISKS (NSD) IN A COMPUTER NETWORK' [patent_app_type] => utility [patent_app_number] => 15/259364 [patent_app_country] => US [patent_app_date] => 2016-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15259364 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/259364
Managing unequal network shared disks (NSD) in a computer network Sep 7, 2016 Issued
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