Search

John M. Winter

Examiner (ID: 13780, Phone: (571)272-6713 , Office: P/3685 )

Most Active Art Unit
3685
Art Unit(s)
3685, 3621
Total Applications
697
Issued Applications
256
Pending Applications
52
Abandoned Applications
389

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14642231 [patent_doc_number] => 10365859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-30 [patent_title] => Storage array management employing a merged background management process [patent_app_type] => utility [patent_app_number] => 14/520034 [patent_app_country] => US [patent_app_date] => 2014-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 10301 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14520034 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/520034
Storage array management employing a merged background management process Oct 20, 2014 Issued
Array ( [id] => 10708774 [patent_doc_number] => 20160054921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'MEMORY MANAGEMENT METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT' [patent_app_type] => utility [patent_app_number] => 14/519138 [patent_app_country] => US [patent_app_date] => 2014-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11717 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14519138 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/519138
Memory management method, memory storage device and memory controlling circuit unit Oct 20, 2014 Issued
Array ( [id] => 11056133 [patent_doc_number] => 20160253094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-01 [patent_title] => 'INFORMATION PROCESSING DEVICE, DATA CACHE DEVICE, INFORMATION PROCESSING METHOD, AND DATA CACHING METHOD' [patent_app_type] => utility [patent_app_number] => 15/030965 [patent_app_country] => US [patent_app_date] => 2014-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 19544 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15030965 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/030965
INFORMATION PROCESSING DEVICE, DATA CACHE DEVICE, INFORMATION PROCESSING METHOD, AND DATA CACHING METHOD Oct 19, 2014 Abandoned
Array ( [id] => 12392844 [patent_doc_number] => 09965196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-08 [patent_title] => Resource reservation for storage system metadata updates [patent_app_type] => utility [patent_app_number] => 14/518157 [patent_app_country] => US [patent_app_date] => 2014-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 20650 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 368 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14518157 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/518157
Resource reservation for storage system metadata updates Oct 19, 2014 Issued
Array ( [id] => 11102869 [patent_doc_number] => 20160299839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-13 [patent_title] => 'CONTROL DEVICE FOR A MOTOR VEHICLE' [patent_app_type] => utility [patent_app_number] => 15/100393 [patent_app_country] => US [patent_app_date] => 2014-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5780 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15100393 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/100393
Control device for a motor vehicle Oct 12, 2014 Issued
Array ( [id] => 15248413 [patent_doc_number] => 10509731 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-17 [patent_title] => Methods and apparatus for memory tier page cache coloring hints [patent_app_type] => utility [patent_app_number] => 14/501096 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 8709 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14501096 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/501096
Methods and apparatus for memory tier page cache coloring hints Sep 29, 2014 Issued
Array ( [id] => 13055307 [patent_doc_number] => 10049046 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-14 [patent_title] => Methods and apparatus for memory tier page cache with zero file [patent_app_type] => utility [patent_app_number] => 14/501112 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 8412 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14501112 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/501112
Methods and apparatus for memory tier page cache with zero file Sep 29, 2014 Issued
Array ( [id] => 13003701 [patent_doc_number] => 10025518 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-17 [patent_title] => Methods and apparatus for system having change identification [patent_app_type] => utility [patent_app_number] => 14/501325 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 9442 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14501325 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/501325
Methods and apparatus for system having change identification Sep 29, 2014 Issued
Array ( [id] => 13291661 [patent_doc_number] => 10157020 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-18 [patent_title] => Optimizing copy processing between storage processors [patent_app_type] => utility [patent_app_number] => 14/501415 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 12501 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 428 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14501415 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/501415
Optimizing copy processing between storage processors Sep 29, 2014 Issued
Array ( [id] => 11917168 [patent_doc_number] => 09785352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-10 [patent_title] => 'Transparent code patching' [patent_app_type] => utility [patent_app_number] => 14/484388 [patent_app_country] => US [patent_app_date] => 2014-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 30 [patent_no_of_words] => 21193 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14484388 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/484388
Transparent code patching Sep 11, 2014 Issued
Array ( [id] => 10732789 [patent_doc_number] => 20160078939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'APPOINTING SEMICONDUCTOR DICE TO ENABLE HIGH STACKING CAPABILITY' [patent_app_type] => utility [patent_app_number] => 14/483260 [patent_app_country] => US [patent_app_date] => 2014-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3101 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14483260 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/483260
APPOINTING SEMICONDUCTOR DICE TO ENABLE HIGH STACKING CAPABILITY Sep 10, 2014 Abandoned
Array ( [id] => 12228943 [patent_doc_number] => 09916189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-13 [patent_title] => 'Concurrently executing critical sections in program code in a processor' [patent_app_type] => utility [patent_app_number] => 14/479297 [patent_app_country] => US [patent_app_date] => 2014-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 10377 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14479297 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/479297
Concurrently executing critical sections in program code in a processor Sep 5, 2014 Issued
Array ( [id] => 10493869 [patent_doc_number] => 20150378891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'MANAGING READ TAGS IN A TRANSACTIONAL MEMORY' [patent_app_type] => utility [patent_app_number] => 14/317370 [patent_app_country] => US [patent_app_date] => 2014-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 21277 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14317370 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/317370
Managing read tags in a transactional memory Jun 26, 2014 Issued
Array ( [id] => 11816887 [patent_doc_number] => 09720837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-01 [patent_title] => 'Allowing non-cacheable loads within a transaction' [patent_app_type] => utility [patent_app_number] => 14/317382 [patent_app_country] => US [patent_app_date] => 2014-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 22133 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 348 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14317382 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/317382
Allowing non-cacheable loads within a transaction Jun 26, 2014 Issued
Array ( [id] => 11903510 [patent_doc_number] => 09772944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'Transactional execution in a multi-processor environment that monitors memory conflicts in a shared cache' [patent_app_type] => utility [patent_app_number] => 14/317376 [patent_app_country] => US [patent_app_date] => 2014-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 19169 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14317376 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/317376
Transactional execution in a multi-processor environment that monitors memory conflicts in a shared cache Jun 26, 2014 Issued
Array ( [id] => 10493873 [patent_doc_number] => 20150378895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'DETECTING CACHE CONFLICTS BY UTILIZING LOGICAL ADDRESS COMPARISONS IN A TRANSACTIONAL MEMORY' [patent_app_type] => utility [patent_app_number] => 14/317394 [patent_app_country] => US [patent_app_date] => 2014-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 20519 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14317394 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/317394
Detecting cache conflicts by utilizing logical address comparisons in a transactional memory Jun 26, 2014 Issued
Array ( [id] => 12453903 [patent_doc_number] => 09983832 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-29 [patent_title] => Storage processor with device cache providing physical memory for guest VM [patent_app_type] => utility [patent_app_number] => 14/317202 [patent_app_country] => US [patent_app_date] => 2014-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4130 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14317202 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/317202
Storage processor with device cache providing physical memory for guest VM Jun 26, 2014 Issued
Array ( [id] => 10493876 [patent_doc_number] => 20150378898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'TRANSACTIONAL EXECUTION PROCESSOR HAVING A CO-PROCESSOR ACCELERATOR, BOTH SHARING A HIGHER LEVEL CACHE' [patent_app_type] => utility [patent_app_number] => 14/317415 [patent_app_country] => US [patent_app_date] => 2014-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 19437 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14317415 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/317415
Transactional execution processor having a co-processor accelerator, both sharing a higher level cache Jun 26, 2014 Issued
Array ( [id] => 10493881 [patent_doc_number] => 20150378902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'CONDITIONAL INCLUSION OF DATA IN A TRANSACTIONAL MEMORY READ SET' [patent_app_type] => utility [patent_app_number] => 14/317391 [patent_app_country] => US [patent_app_date] => 2014-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 22008 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14317391 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/317391
Conditional inclusion of data in a transactional memory read set Jun 26, 2014 Issued
Array ( [id] => 9794880 [patent_doc_number] => 20150006824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'APPARATUS AND METHOD OF DETECTING PERIODICITY OF MEMORY' [patent_app_type] => utility [patent_app_number] => 14/317209 [patent_app_country] => US [patent_app_date] => 2014-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4386 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14317209 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/317209
APPARATUS AND METHOD OF DETECTING PERIODICITY OF MEMORY Jun 26, 2014 Abandoned
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