Search

John M. Zaleskas

Examiner (ID: 19026, Phone: (571)272-5958 , Office: P/3747 )

Most Active Art Unit
3747
Art Unit(s)
3747
Total Applications
711
Issued Applications
422
Pending Applications
59
Abandoned Applications
240

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6326119 [patent_doc_number] => 20100326970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'Manufacturing Apparatus of Semiconductor Device and Method for Manufacturing Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 12/878461 [patent_app_country] => US [patent_app_date] => 2010-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7887 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0326/20100326970.pdf [firstpage_image] =>[orig_patent_app_number] => 12878461 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/878461
Manufacturing apparatus for selectively removing one or more material layers by laser ablation Sep 8, 2010 Issued
Array ( [id] => 6327720 [patent_doc_number] => 20100327355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'FRONT AND BACKSIDE PROCESSED THIN FILM ELECTRONIC DEVICES' [patent_app_type] => utility [patent_app_number] => 12/877269 [patent_app_country] => US [patent_app_date] => 2010-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4600 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0327/20100327355.pdf [firstpage_image] =>[orig_patent_app_number] => 12877269 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/877269
Front and backside processed thin film electronic devices Sep 7, 2010 Issued
Array ( [id] => 7804591 [patent_doc_number] => 20120055543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-08 [patent_title] => 'BACK CONTACT DIFFUSION BARRIER LAYERS FOR GROUP IBIIIAVIA PHOTOVOLTAIC CELLS' [patent_app_type] => utility [patent_app_number] => 12/875669 [patent_app_country] => US [patent_app_date] => 2010-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3411 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20120055543.pdf [firstpage_image] =>[orig_patent_app_number] => 12875669 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/875669
Back contact diffusion barrier layers for group ibiiiavia photovoltaic cells Sep 2, 2010 Issued
Array ( [id] => 6348416 [patent_doc_number] => 20100330769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'Semiconductor device and method of manufacturing thereof' [patent_app_type] => utility [patent_app_number] => 12/923117 [patent_app_country] => US [patent_app_date] => 2010-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 12282 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0330/20100330769.pdf [firstpage_image] =>[orig_patent_app_number] => 12923117 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/923117
Method of manufacturing semiconductor device with lower capacitor electrode that includes islands of conductive oxide films arranged on a noble metal film Sep 1, 2010 Issued
Array ( [id] => 5980317 [patent_doc_number] => 20110095424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-28 [patent_title] => 'SEMICONDUCTOR PACKAGE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/855322 [patent_app_country] => US [patent_app_date] => 2010-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13157 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20110095424.pdf [firstpage_image] =>[orig_patent_app_number] => 12855322 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/855322
Semiconductor package structure having plural packages in a stacked arrangement Aug 11, 2010 Issued
Array ( [id] => 7740360 [patent_doc_number] => 08105926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-31 [patent_title] => 'Method for producing a semiconductor device by plasma doping a semiconductor region to form an impurity region' [patent_app_type] => utility [patent_app_number] => 12/853840 [patent_app_country] => US [patent_app_date] => 2010-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 36 [patent_no_of_words] => 16910 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/105/08105926.pdf [firstpage_image] =>[orig_patent_app_number] => 12853840 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/853840
Method for producing a semiconductor device by plasma doping a semiconductor region to form an impurity region Aug 9, 2010 Issued
Array ( [id] => 6555290 [patent_doc_number] => 20100288994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-18 [patent_title] => 'METHOD OF FORMING MEMORY CELL USING GAS CLUSTER ION BEAMS' [patent_app_type] => utility [patent_app_number] => 12/844541 [patent_app_country] => US [patent_app_date] => 2010-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 2879 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20100288994.pdf [firstpage_image] =>[orig_patent_app_number] => 12844541 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/844541
Memory cell having GeN-containing material and variable resistance material embedded within insulating material Jul 26, 2010 Issued
Array ( [id] => 6192654 [patent_doc_number] => 20110024408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-03 [patent_title] => 'DEFOGGING DEVICE WITH CARBON NANOTUBE FILM' [patent_app_type] => utility [patent_app_number] => 12/843058 [patent_app_country] => US [patent_app_date] => 2010-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1574 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20110024408.pdf [firstpage_image] =>[orig_patent_app_number] => 12843058 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/843058
Defogging device with carbon nanotube film Jul 25, 2010 Issued
Array ( [id] => 8555075 [patent_doc_number] => 08329547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-11 [patent_title] => 'Semiconductor process for etching a recess into a substrate by using an etchant that contains hydrogen peroxide' [patent_app_type] => utility [patent_app_number] => 12/841174 [patent_app_country] => US [patent_app_date] => 2010-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2270 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12841174 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/841174
Semiconductor process for etching a recess into a substrate by using an etchant that contains hydrogen peroxide Jul 21, 2010 Issued
Array ( [id] => 6446744 [patent_doc_number] => 20100283158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'STRUCTURE AND METHOD FOR FORMING A CAPACITIVELY COUPLED CHIP-TO-CHIP SIGNALING INTERFACE' [patent_app_type] => utility [patent_app_number] => 12/841846 [patent_app_country] => US [patent_app_date] => 2010-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3262 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20100283158.pdf [firstpage_image] =>[orig_patent_app_number] => 12841846 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/841846
Structure and method for forming a capacitively coupled chip-to-chip signaling interface Jul 21, 2010 Issued
Array ( [id] => 6196160 [patent_doc_number] => 20110027918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-03 [patent_title] => 'INSPECTION METHOD AND MANUFACTURING METHOD OF LIGHT-EMITTING DEVICE' [patent_app_type] => utility [patent_app_number] => 12/841394 [patent_app_country] => US [patent_app_date] => 2010-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 17451 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20110027918.pdf [firstpage_image] =>[orig_patent_app_number] => 12841394 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/841394
Inspection method and manufacturing method of light-emitting device Jul 21, 2010 Issued
Array ( [id] => 7564879 [patent_doc_number] => 20110284942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-24 [patent_title] => 'SEMICONDUCTOR DEVICE WITH BURIED BIT LINES AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/841845 [patent_app_country] => US [patent_app_date] => 2010-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6776 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20110284942.pdf [firstpage_image] =>[orig_patent_app_number] => 12841845 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/841845
Method of fabricating semiconductor device with buried bit line Jul 21, 2010 Issued
Array ( [id] => 7738856 [patent_doc_number] => 20120018832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-26 [patent_title] => 'METHODS, STRUCTURES, AND DESIGN STRUCTURES FOR IMPROVED ADHESION OF PROTECTIVE LAYERS OF IMAGER MICROLENS STRUCTURES' [patent_app_type] => utility [patent_app_number] => 12/841750 [patent_app_country] => US [patent_app_date] => 2010-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5782 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20120018832.pdf [firstpage_image] =>[orig_patent_app_number] => 12841750 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/841750
Methods for improved adhesion of protective layers of imager microlens structures by forming an interfacial region Jul 21, 2010 Issued
Array ( [id] => 6196221 [patent_doc_number] => 20110027979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-03 [patent_title] => 'DIELECTRIC FILM, METHOD OF MANUFACUTRING SEMICONDUCTOR DEVICE USING DIELECTRIC FILM, AND SEMICONDUCTOR MANUFACTURING APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/840602 [patent_app_country] => US [patent_app_date] => 2010-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9415 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20110027979.pdf [firstpage_image] =>[orig_patent_app_number] => 12840602 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/840602
Method of manufacturing hafnium-containing and silicon-containing metal oxynitride dielectric film Jul 20, 2010 Issued
Array ( [id] => 8421708 [patent_doc_number] => 08278196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-02 [patent_title] => 'High surface dopant concentration semiconductor device and method of fabricating' [patent_app_type] => utility [patent_app_number] => 12/840830 [patent_app_country] => US [patent_app_date] => 2010-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4462 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12840830 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/840830
High surface dopant concentration semiconductor device and method of fabricating Jul 20, 2010 Issued
Array ( [id] => 8549208 [patent_doc_number] => 08324089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-04 [patent_title] => 'Compositions for forming doped regions in semiconductor substrates, methods for fabricating such compositions, and methods for forming doped regions using such compositions' [patent_app_type] => utility [patent_app_number] => 12/839924 [patent_app_country] => US [patent_app_date] => 2010-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 7855 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12839924 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/839924
Compositions for forming doped regions in semiconductor substrates, methods for fabricating such compositions, and methods for forming doped regions using such compositions Jul 19, 2010 Issued
Array ( [id] => 6149397 [patent_doc_number] => 20110020992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'Integrated Nanostructure-Based Non-Volatile Memory Fabrication' [patent_app_type] => utility [patent_app_number] => 12/840081 [patent_app_country] => US [patent_app_date] => 2010-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 16041 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20110020992.pdf [firstpage_image] =>[orig_patent_app_number] => 12840081 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/840081
Integrated nanostructure-based non-volatile memory fabrication Jul 19, 2010 Issued
Array ( [id] => 8028091 [patent_doc_number] => 08143128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'Multilayer dielectric defect method' [patent_app_type] => utility [patent_app_number] => 12/833354 [patent_app_country] => US [patent_app_date] => 2010-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 8767 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/143/08143128.pdf [firstpage_image] =>[orig_patent_app_number] => 12833354 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/833354
Multilayer dielectric defect method Jul 8, 2010 Issued
Array ( [id] => 6534714 [patent_doc_number] => 20100270680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKING AND ANTI-FLASH STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/831822 [patent_app_country] => US [patent_app_date] => 2010-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6889 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20100270680.pdf [firstpage_image] =>[orig_patent_app_number] => 12831822 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/831822
Integrated circuit package system with offset stacking and anti-flash structure Jul 6, 2010 Issued
Array ( [id] => 9081525 [patent_doc_number] => 20130267055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-10 [patent_title] => 'DEPOSITION SUBSTRATE OF DEPOSITION APPARATUS, METHOD OF FORMING LAYER USING THE SAME, AND METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/988875 [patent_app_country] => US [patent_app_date] => 2010-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7416 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13988875 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/988875
Deposition substrate of deposition apparatus, method of forming layer using the same, and method of manufacturing organic light emitting diode display device Jul 6, 2010 Issued
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