Search

John Moore Jain Macilwinen

Examiner (ID: 2498, Phone: (571)272-9686 , Office: P/2442 )

Most Active Art Unit
2442
Art Unit(s)
2442, 2142
Total Applications
749
Issued Applications
477
Pending Applications
51
Abandoned Applications
221

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12061879 [patent_doc_number] => 20170338223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'SINGLE MASK LEVEL INCLUDING A RESISTOR AND A THROUGH-GATE IMPLANT' [patent_app_type] => utility [patent_app_number] => 15/669246 [patent_app_country] => US [patent_app_date] => 2017-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3789 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15669246 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/669246
Single mask level including a resistor and a through-gate implant Aug 3, 2017 Issued
Array ( [id] => 12243452 [patent_doc_number] => 20180076315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/666529 [patent_app_country] => US [patent_app_date] => 2017-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 17336 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15666529 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/666529
Semiconductor device and method of manufacturing semiconductor device Jul 31, 2017 Issued
Array ( [id] => 13043399 [patent_doc_number] => 10043841 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-07 [patent_title] => Image sensor device and method for forming the same [patent_app_type] => utility [patent_app_number] => 15/663985 [patent_app_country] => US [patent_app_date] => 2017-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4974 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15663985 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/663985
Image sensor device and method for forming the same Jul 30, 2017 Issued
Array ( [id] => 13862043 [patent_doc_number] => 10192746 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-29 [patent_title] => STI inner spacer to mitigate SDB loading [patent_app_type] => utility [patent_app_number] => 15/665183 [patent_app_country] => US [patent_app_date] => 2017-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 4433 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15665183 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/665183
STI inner spacer to mitigate SDB loading Jul 30, 2017 Issued
Array ( [id] => 12478134 [patent_doc_number] => 09991300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Buried channel deeply depleted channel transistor [patent_app_type] => utility [patent_app_number] => 15/658907 [patent_app_country] => US [patent_app_date] => 2017-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6965 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15658907 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/658907
Buried channel deeply depleted channel transistor Jul 24, 2017 Issued
Array ( [id] => 13201411 [patent_doc_number] => 10115626 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-30 [patent_title] => Methods for forming isolation blocks of semiconductor devices, semiconductor devices and methods for manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/651114 [patent_app_country] => US [patent_app_date] => 2017-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 4863 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15651114 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/651114
Methods for forming isolation blocks of semiconductor devices, semiconductor devices and methods for manufacturing the same Jul 16, 2017 Issued
Array ( [id] => 12005641 [patent_doc_number] => 20170309796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-26 [patent_title] => 'LIGHT EMITTING DIODE PACKAGE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/645632 [patent_app_country] => US [patent_app_date] => 2017-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15645632 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/645632
Light emitting diode package and manufacturing method thereof Jul 9, 2017 Issued
Array ( [id] => 13799569 [patent_doc_number] => 20190013323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => INTEGRATED COMPUTING STRUCTURES FORMED ON SILICON [patent_app_type] => utility [patent_app_number] => 15/641558 [patent_app_country] => US [patent_app_date] => 2017-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7341 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15641558 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/641558
Integrated computing structures formed on silicon Jul 4, 2017 Issued
Array ( [id] => 11983721 [patent_doc_number] => 20170287876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'METHOD AND DEVICE FOR CONTROLLING OPERATION USING TEMPERATURE DEVIATION IN MULTI-CHIP PACKAGE' [patent_app_type] => utility [patent_app_number] => 15/620978 [patent_app_country] => US [patent_app_date] => 2017-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 14898 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15620978 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/620978
Method and device for controlling operation using temperature deviation in multi-chip package Jun 12, 2017 Issued
Array ( [id] => 12355437 [patent_doc_number] => 09953992 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-24 [patent_title] => Mid-plane word line switch connection for CMOS under three-dimensional memory device and method of making thereof [patent_app_type] => utility [patent_app_number] => 15/611220 [patent_app_country] => US [patent_app_date] => 2017-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 48 [patent_no_of_words] => 17395 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15611220 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/611220
Mid-plane word line switch connection for CMOS under three-dimensional memory device and method of making thereof May 31, 2017 Issued
Array ( [id] => 12535422 [patent_doc_number] => 10008668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-26 [patent_title] => Thermally optimized phase change memory cells and methods of fabricating the same [patent_app_type] => utility [patent_app_number] => 15/607095 [patent_app_country] => US [patent_app_date] => 2017-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 11689 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15607095 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/607095
Thermally optimized phase change memory cells and methods of fabricating the same May 25, 2017 Issued
Array ( [id] => 11952296 [patent_doc_number] => 20170256447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'INSULATING A VIA IN A SEMICONDUCTOR SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 15/601488 [patent_app_country] => US [patent_app_date] => 2017-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1925 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15601488 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/601488
Insulating a via in a semiconductor substrate May 21, 2017 Issued
Array ( [id] => 14299323 [patent_doc_number] => 10289789 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => System for designing integrated circuit layout and method of making the integrated circuit layout [patent_app_type] => utility [patent_app_number] => 15/601697 [patent_app_country] => US [patent_app_date] => 2017-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3475 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15601697 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/601697
System for designing integrated circuit layout and method of making the integrated circuit layout May 21, 2017 Issued
Array ( [id] => 16234136 [patent_doc_number] => 10741700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/604092 [patent_app_country] => US [patent_app_date] => 2017-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4742 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16604092 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/604092
Semiconductor device May 17, 2017 Issued
Array ( [id] => 16432931 [patent_doc_number] => 10833028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Thin-film capacitor structure and semiconductor device including the thin-film capacitor structure [patent_app_type] => utility [patent_app_number] => 16/603934 [patent_app_country] => US [patent_app_date] => 2017-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5278 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16603934 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/603934
Thin-film capacitor structure and semiconductor device including the thin-film capacitor structure May 16, 2017 Issued
Array ( [id] => 12062094 [patent_doc_number] => 20170338438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'Organic Light Emitting Display Device' [patent_app_type] => utility [patent_app_number] => 15/592844 [patent_app_country] => US [patent_app_date] => 2017-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9060 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15592844 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/592844
Organic light emitting display device May 10, 2017 Issued
Array ( [id] => 12054721 [patent_doc_number] => 20170331065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'Light-Emitting Element, Light-Emitting Device, Electronic Device, and Lighting Device' [patent_app_type] => utility [patent_app_number] => 15/590280 [patent_app_country] => US [patent_app_date] => 2017-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 28579 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15590280 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/590280
Light-emitting element, light-emitting device, electronic device, and lighting device May 8, 2017 Issued
Array ( [id] => 13485793 [patent_doc_number] => 20180294439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => FLEXIBLE DISPLAY PANELS AND MANUFACTURING METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 15/567566 [patent_app_country] => US [patent_app_date] => 2017-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3049 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15567566 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/567566
Flexible display panels and manufacturing methods thereof May 2, 2017 Issued
Array ( [id] => 11854958 [patent_doc_number] => 20170229450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-10 [patent_title] => 'FIELD EFFECT TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 15/499222 [patent_app_country] => US [patent_app_date] => 2017-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8132 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15499222 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/499222
FIELD EFFECT TRANSISTORS Apr 26, 2017 Abandoned
Array ( [id] => 15109113 [patent_doc_number] => 10475888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Integration of III-V devices on Si wafers [patent_app_type] => utility [patent_app_number] => 15/492785 [patent_app_country] => US [patent_app_date] => 2017-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 31 [patent_no_of_words] => 11335 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15492785 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/492785
Integration of III-V devices on Si wafers Apr 19, 2017 Issued
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