John Moore Jain Macilwinen

Array ( [id] => 12314910 [patent_doc_number] => 09941356 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-10 [patent_title] => JFET and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 15/492805 [patent_app_country] => US [patent_app_date] => 2017-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3864 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15492805 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13667345 [patent_doc_number] => 10163851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Tri-layer CoWoS structure [patent_app_type] => utility [patent_app_number] => 15/488933 [patent_app_country] => US [patent_app_date] => 2017-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4689 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15488933 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13131941 [patent_doc_number] => 10083910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-25 [patent_title] => Backside contacts for integrated circuit devices [patent_app_type] => utility [patent_app_number] => 15/479493 [patent_app_country] => US [patent_app_date] => 2017-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3181 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15479493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12554511 [patent_doc_number] => 10014395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Fin tunnel field effect transistor (FET) [patent_app_type] => utility [patent_app_number] => 15/478198 [patent_app_country] => US [patent_app_date] => 2017-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 7219 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15478198 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12250186 [patent_doc_number] => 09922968 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-20 [patent_title] => 'Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells' [patent_app_type] => utility [patent_app_number] => 15/475198 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 114 [patent_figures_cnt] => 219 [patent_no_of_words] => 52597 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 444 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15475198 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12250313 [patent_doc_number] => 09923096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Gate-all-around fin device' [patent_app_type] => utility [patent_app_number] => 15/474096 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3567 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15474096 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12779341 [patent_doc_number] => 20180151615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => CMOS IMAGE SENSOR WITH DUAL DAMASCENE GRID DESIGN HAVING ABSORPTION ENHANCEMENT STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/469782 [patent_app_country] => US [patent_app_date] => 2017-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7610 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15469782 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13132227 [patent_doc_number] => 10084053 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-09-25 [patent_title] => Gate cuts after metal gate formation [patent_app_type] => utility [patent_app_number] => 15/470205 [patent_app_country] => US [patent_app_date] => 2017-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 3924 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15470205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11971000 [patent_doc_number] => 20170275154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'Atomic Layer Deposition Layer for a Microelectromechanical system (MEMS) Device' [patent_app_type] => utility [patent_app_number] => 15/470342 [patent_app_country] => US [patent_app_date] => 2017-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 4477 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15470342 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12054580 [patent_doc_number] => 20170330923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'TRANSPARENT DISPLAY DEVICE AND METHOD OF MANUFACTURING A TRANSPARENT DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/447798 [patent_app_country] => US [patent_app_date] => 2017-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 14980 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15447798 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11939813 [patent_doc_number] => 20170243964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/434199 [patent_app_country] => US [patent_app_date] => 2017-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7885 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15434199 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11869575 [patent_doc_number] => 20170236861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'OPTICAL FILTER ARRAY' [patent_app_type] => utility [patent_app_number] => 15/428869 [patent_app_country] => US [patent_app_date] => 2017-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5965 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15428869 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12147704 [patent_doc_number] => 09881964 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-30 [patent_title] => 'Image sensor with inverted source follower' [patent_app_type] => utility [patent_app_number] => 15/427748 [patent_app_country] => US [patent_app_date] => 2017-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3062 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15427748 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11869749 [patent_doc_number] => 20170237033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'ELECTRO-OPTICAL APPARATUS AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 15/427634 [patent_app_country] => US [patent_app_date] => 2017-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13014 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15427634 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14151703 [patent_doc_number] => 10256241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Vertical thyristor memory with minority carrier lifetime reduction [patent_app_type] => utility [patent_app_number] => 15/426972 [patent_app_country] => US [patent_app_date] => 2017-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 38 [patent_no_of_words] => 11827 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15426972 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12458067 [patent_doc_number] => 09985228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-29 [patent_title] => Display device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/421820 [patent_app_country] => US [patent_app_date] => 2017-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4178 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15421820 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13132175 [patent_doc_number] => 10084027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-25 [patent_title] => Display panel and method of manufacturing same [patent_app_type] => utility [patent_app_number] => 15/413797 [patent_app_country] => US [patent_app_date] => 2017-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 14368 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15413797 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14363381 [patent_doc_number] => 10302989 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Method for improving transmittance of flat or curved liquid crystal display panel [patent_app_type] => utility [patent_app_number] => 15/500206 [patent_app_country] => US [patent_app_date] => 2017-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 2407 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15500206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11911200 [patent_doc_number] => 09780021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Method of manufacturing element chip, method of manufacturing electronic component-mounted structure, and electronic component-mounted structure' [patent_app_type] => utility [patent_app_number] => 15/408770 [patent_app_country] => US [patent_app_date] => 2017-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 27 [patent_no_of_words] => 7898 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 362 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15408770 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12498681 [patent_doc_number] => 09997521 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => Semiconductor devices [patent_app_type] => utility [patent_app_number] => 15/405808 [patent_app_country] => US [patent_app_date] => 2017-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 9929 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15405808 [rel_patent_id] =>[rel_patent_doc_number] =>)