Search

John Moore Jain Macilwinen

Examiner (ID: 2498, Phone: (571)272-9686 , Office: P/2442 )

Most Active Art Unit
2442
Art Unit(s)
2442, 2142
Total Applications
749
Issued Applications
477
Pending Applications
51
Abandoned Applications
221

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9112975 [patent_doc_number] => 08569145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'Semiconductor device and method of producing the same' [patent_app_type] => utility [patent_app_number] => 13/646527 [patent_app_country] => US [patent_app_date] => 2012-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 5695 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13646527 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/646527
Semiconductor device and method of producing the same Oct 4, 2012 Issued
Array ( [id] => 8615310 [patent_doc_number] => 20130020621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-24 [patent_title] => 'SOLID-STATE IMAGING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/626612 [patent_app_country] => US [patent_app_date] => 2012-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8507 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13626612 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/626612
Solid-state imaging device Sep 24, 2012 Issued
Array ( [id] => 8603854 [patent_doc_number] => 20130009166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-10 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/620088 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 21245 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13620088 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/620088
Semiconductor device Sep 13, 2012 Issued
Array ( [id] => 8586268 [patent_doc_number] => 20130005089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'Wafer Level Package For Heat Dissipation And Method Of Manufacturing The Same' [patent_app_type] => utility [patent_app_number] => 13/607393 [patent_app_country] => US [patent_app_date] => 2012-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4256 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13607393 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/607393
Wafer Level Package For Heat Dissipation And Method Of Manufacturing The Same Sep 6, 2012 Abandoned
Array ( [id] => 9469628 [patent_doc_number] => 08723262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-13 [patent_title] => 'SOI FinFET with recessed merged fins and liner for enhanced stress coupling' [patent_app_type] => utility [patent_app_number] => 13/606893 [patent_app_country] => US [patent_app_date] => 2012-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 7433 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13606893 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/606893
SOI FinFET with recessed merged fins and liner for enhanced stress coupling Sep 6, 2012 Issued
Array ( [id] => 9232694 [patent_doc_number] => 08597998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-03 [patent_title] => 'Power MOS device fabrication' [patent_app_type] => utility [patent_app_number] => 13/604286 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 4092 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13604286 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/604286
Power MOS device fabrication Sep 4, 2012 Issued
Array ( [id] => 9818287 [patent_doc_number] => 08928075 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-06 [patent_title] => 'Power integrated circuit including series-connected source substrate and drain substrate power MOSFETs' [patent_app_type] => utility [patent_app_number] => 13/563923 [patent_app_country] => US [patent_app_date] => 2012-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6114 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13563923 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/563923
Power integrated circuit including series-connected source substrate and drain substrate power MOSFETs Jul 31, 2012 Issued
Array ( [id] => 9273437 [patent_doc_number] => 08637368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-28 [patent_title] => 'Fabrication of MOS device with varying trench depth' [patent_app_type] => utility [patent_app_number] => 13/559975 [patent_app_country] => US [patent_app_date] => 2012-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 43 [patent_no_of_words] => 5841 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13559975 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/559975
Fabrication of MOS device with varying trench depth Jul 26, 2012 Issued
Array ( [id] => 9944783 [patent_doc_number] => 08994085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-31 [patent_title] => 'Integrated circuit including DRAM and SRAM/logic' [patent_app_type] => utility [patent_app_number] => 13/551714 [patent_app_country] => US [patent_app_date] => 2012-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 7321 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13551714 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/551714
Integrated circuit including DRAM and SRAM/logic Jul 17, 2012 Issued
Array ( [id] => 9220168 [patent_doc_number] => 20140014943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'AMORPHOUS PHASE YTTRIUM-DOPED INDIUM ZINC OXIDE THIN FILM TRANSISTORS AND METHOD FOR MAKING SAME' [patent_app_type] => utility [patent_app_number] => 13/549844 [patent_app_country] => US [patent_app_date] => 2012-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 13769 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13549844 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/549844
AMORPHOUS PHASE YTTRIUM-DOPED INDIUM ZINC OXIDE THIN FILM TRANSISTORS AND METHOD FOR MAKING SAME Jul 15, 2012 Abandoned
Array ( [id] => 10831910 [patent_doc_number] => 08860082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-14 [patent_title] => 'Transient voltage suppressor circuit, and diode device therefor and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 13/549501 [patent_app_country] => US [patent_app_date] => 2012-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 3427 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13549501 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/549501
Transient voltage suppressor circuit, and diode device therefor and manufacturing method thereof Jul 14, 2012 Issued
Array ( [id] => 9923528 [patent_doc_number] => 08981497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-17 [patent_title] => 'Chip package structure and method for forming the same' [patent_app_type] => utility [patent_app_number] => 13/548663 [patent_app_country] => US [patent_app_date] => 2012-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1555 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13548663 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/548663
Chip package structure and method for forming the same Jul 12, 2012 Issued
Array ( [id] => 10851682 [patent_doc_number] => 08878369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-04 [patent_title] => 'Low power/high speed TSV interface design' [patent_app_type] => utility [patent_app_number] => 13/546024 [patent_app_country] => US [patent_app_date] => 2012-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2039 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13546024 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/546024
Low power/high speed TSV interface design Jul 10, 2012 Issued
Array ( [id] => 9220239 [patent_doc_number] => 20140015014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'FIELD EFFECT TRANSISTORS WITH VARYING THRESHOLD VOLTAGES' [patent_app_type] => utility [patent_app_number] => 13/545224 [patent_app_country] => US [patent_app_date] => 2012-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7991 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13545224 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/545224
Field effect transistors with varying threshold voltages Jul 9, 2012 Issued
Array ( [id] => 10851563 [patent_doc_number] => 08878248 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-04 [patent_title] => 'Semiconductor device and fabrication method' [patent_app_type] => utility [patent_app_number] => 13/544023 [patent_app_country] => US [patent_app_date] => 2012-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 6521 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13544023 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/544023
Semiconductor device and fabrication method Jul 8, 2012 Issued
Array ( [id] => 8603950 [patent_doc_number] => 20130009262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-10 [patent_title] => 'NEUTRON DETECTION USING GD-LOADED OXIDE AND NITRIDE HETEROJUNCTION DIODES' [patent_app_type] => utility [patent_app_number] => 13/541923 [patent_app_country] => US [patent_app_date] => 2012-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5375 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13541923 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/541923
Neutron detection using GD-loaded oxide and nitride heterojunction diodes Jul 4, 2012 Issued
Array ( [id] => 9209481 [patent_doc_number] => 20140008658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'Stress-Controlled HEMT' [patent_app_type] => utility [patent_app_number] => 13/540711 [patent_app_country] => US [patent_app_date] => 2012-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3884 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13540711 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/540711
Stress-controlled HEMT Jul 2, 2012 Issued
Array ( [id] => 9875992 [patent_doc_number] => 08963264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Magnetic stack with orthogonal biasing layer' [patent_app_type] => utility [patent_app_number] => 13/539063 [patent_app_country] => US [patent_app_date] => 2012-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3262 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13539063 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/539063
Magnetic stack with orthogonal biasing layer Jun 28, 2012 Issued
Array ( [id] => 9205520 [patent_doc_number] => 20140004697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGING' [patent_app_type] => utility [patent_app_number] => 13/534289 [patent_app_country] => US [patent_app_date] => 2012-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2310 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13534289 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/534289
Method of manufacturing semiconductor packaging Jun 26, 2012 Issued
Array ( [id] => 8582946 [patent_doc_number] => 20130001767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'PACKAGE AND METHOD FOR MANUFACTURING PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/534409 [patent_app_country] => US [patent_app_date] => 2012-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6435 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13534409 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/534409
PACKAGE AND METHOD FOR MANUFACTURING PACKAGE Jun 26, 2012 Abandoned
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