John P. Dulka

Array ( [id] => 20053746 [patent_doc_number] => 20250191968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => BONDING SYSTEM WITH SEALING GASKET AND METHOD FOR USING THE SAME [patent_app_type] => utility [patent_app_number] => 19/040693 [patent_app_country] => US [patent_app_date] => 2025-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19040693 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20019711 [patent_doc_number] => 20250157933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 19/022942 [patent_app_country] => US [patent_app_date] => 2025-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23997 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19022942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20120915 [patent_doc_number] => 20250235946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => PORTABLE BATTERY PACK-POWERED WELDER [patent_app_type] => utility [patent_app_number] => 19/018545 [patent_app_country] => US [patent_app_date] => 2025-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3455 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19018545 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20360163 [patent_doc_number] => 12476168 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => 3D semiconductor device and structure with three levels and isolation layers [patent_app_type] => utility [patent_app_number] => 18/778977 [patent_app_country] => US [patent_app_date] => 2024-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 73 [patent_figures_cnt] => 74 [patent_no_of_words] => 15374 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778977 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19467943 [patent_doc_number] => 20240321613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => SYSTEMS AND METHODS FOR SYSTEMATIC PHYSICAL FAILURE ANALYSIS (PFA) FAULT LOCALIZATION [patent_app_type] => utility [patent_app_number] => 18/679252 [patent_app_country] => US [patent_app_date] => 2024-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18679252 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19964944 [patent_doc_number] => 12334464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Encapsulated package including device dies connected via interconnect die [patent_app_type] => utility [patent_app_number] => 18/629641 [patent_app_country] => US [patent_app_date] => 2024-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 2076 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629641 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19419568 [patent_doc_number] => 20240295691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => MULTILEVEL SEMICONDUCTOR DEVICE AND STRUCTURE WITH OXIDE BONDING [patent_app_type] => utility [patent_app_number] => 18/622867 [patent_app_country] => US [patent_app_date] => 2024-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14703 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18622867 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19419568 [patent_doc_number] => 20240295691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => MULTILEVEL SEMICONDUCTOR DEVICE AND STRUCTURE WITH OXIDE BONDING [patent_app_type] => utility [patent_app_number] => 18/622867 [patent_app_country] => US [patent_app_date] => 2024-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14703 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18622867 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19337165 [patent_doc_number] => 20240251595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => ELECTRONIC APPARATUS AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/604923 [patent_app_country] => US [patent_app_date] => 2024-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604923 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19337165 [patent_doc_number] => 20240251595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => ELECTRONIC APPARATUS AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/604923 [patent_app_country] => US [patent_app_date] => 2024-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604923 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20267136 [patent_doc_number] => 12438135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Multilayer power, converter with devices having reduced lateral current [patent_app_type] => utility [patent_app_number] => 18/432387 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 28 [patent_no_of_words] => 2087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18432387 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20267136 [patent_doc_number] => 12438135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Multilayer power, converter with devices having reduced lateral current [patent_app_type] => utility [patent_app_number] => 18/432387 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 28 [patent_no_of_words] => 2087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18432387 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20267136 [patent_doc_number] => 12438135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Multilayer power, converter with devices having reduced lateral current [patent_app_type] => utility [patent_app_number] => 18/432387 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 28 [patent_no_of_words] => 2087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18432387 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19130821 [patent_doc_number] => 20240136174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => INTEGRATED STEALTH LASER FOR WAFER EDGE TRIMMING PROCESS [patent_app_type] => utility [patent_app_number] => 18/402991 [patent_app_country] => US [patent_app_date] => 2024-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9054 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402991 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19873865 [patent_doc_number] => 12266739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Solid state transducer dies having reflective features over contacts and associated systems and methods [patent_app_type] => utility [patent_app_number] => 18/401212 [patent_app_country] => US [patent_app_date] => 2023-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 3355 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18401212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19414793 [patent_doc_number] => 12080630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => 3D semiconductor device and structure with metal layers and a connective path [patent_app_type] => utility [patent_app_number] => 18/534433 [patent_app_country] => US [patent_app_date] => 2023-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 73 [patent_figures_cnt] => 74 [patent_no_of_words] => 20979 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18534433 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19858243 [patent_doc_number] => 12261094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Semiconductor device including lead with varying thickness [patent_app_type] => utility [patent_app_number] => 18/515837 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 12812 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18515837 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19168524 [patent_doc_number] => 11984438 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Multilevel semiconductor device and structure with oxide bonding [patent_app_type] => utility [patent_app_number] => 18/388848 [patent_app_country] => US [patent_app_date] => 2023-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 51 [patent_no_of_words] => 14432 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18388848 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18991284 [patent_doc_number] => 20240063253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => METAL-INSULATOR-METAL CAPACITORS AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/501396 [patent_app_country] => US [patent_app_date] => 2023-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13388 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18501396 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19858268 [patent_doc_number] => 12261119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Method for manufacturing semiconductor device with impurity doped oxide semiconductor layer [patent_app_type] => utility [patent_app_number] => 18/370916 [patent_app_country] => US [patent_app_date] => 2023-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 71 [patent_no_of_words] => 29062 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18370916 [rel_patent_id] =>[rel_patent_doc_number] =>)