Search

John P. Dulka

Examiner (ID: 8652, Phone: (571)270-7398 , Office: P/2895 )

Most Active Art Unit
2895
Art Unit(s)
2817, 2895
Total Applications
1010
Issued Applications
820
Pending Applications
90
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17064825 [patent_doc_number] => 11109452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-31 [patent_title] => Modular LED heater [patent_app_type] => utility [patent_app_number] => 16/683564 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 6557 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16683564 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/683564
Modular LED heater Nov 13, 2019 Issued
Array ( [id] => 16226241 [patent_doc_number] => 20200251358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/683753 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10034 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16683753 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/683753
Semiconductor device manufacturing apparatus including laser module Nov 13, 2019 Issued
Array ( [id] => 15625901 [patent_doc_number] => 20200083355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => FIN CUT ETCH PROCESS FOR VERTICAL TRANSISTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/682604 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4829 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682604 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/682604
Fin cut etch process for vertical transistor devices Nov 12, 2019 Issued
Array ( [id] => 16827866 [patent_doc_number] => 20210143159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => STACKED VERTICAL TRANSISTOR MEMORY CELL WITH EPI CONNECTIONS [patent_app_type] => utility [patent_app_number] => 16/680965 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6583 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16680965 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/680965
Stacked vertical transistor memory cell with epi connections Nov 11, 2019 Issued
Array ( [id] => 18874931 [patent_doc_number] => 11862756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Solid state transducer dies having reflective features over contacts and associated systems and methods [patent_app_type] => utility [patent_app_number] => 16/673092 [patent_app_country] => US [patent_app_date] => 2019-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 3327 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16673092 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/673092
Solid state transducer dies having reflective features over contacts and associated systems and methods Nov 3, 2019 Issued
Array ( [id] => 17324914 [patent_doc_number] => 11215921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Residual layer thickness compensation in nano-fabrication by modified drop pattern [patent_app_type] => utility [patent_app_number] => 16/670497 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 17352 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16670497 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/670497
Residual layer thickness compensation in nano-fabrication by modified drop pattern Oct 30, 2019 Issued
Array ( [id] => 16098329 [patent_doc_number] => 20200203151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => METHOD OF HEATING SOC FILM ON WAFER AND HEATING APPARATUS USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/667802 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4298 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667802 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/667802
Method of heating SOC film on wafer by electromagnetic wave generator and heating apparatus using the same Oct 28, 2019 Issued
Array ( [id] => 16098329 [patent_doc_number] => 20200203151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => METHOD OF HEATING SOC FILM ON WAFER AND HEATING APPARATUS USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/667802 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4298 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667802 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/667802
Method of heating SOC film on wafer by electromagnetic wave generator and heating apparatus using the same Oct 28, 2019 Issued
Array ( [id] => 16098329 [patent_doc_number] => 20200203151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => METHOD OF HEATING SOC FILM ON WAFER AND HEATING APPARATUS USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/667802 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4298 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667802 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/667802
Method of heating SOC film on wafer by electromagnetic wave generator and heating apparatus using the same Oct 28, 2019 Issued
Array ( [id] => 16098329 [patent_doc_number] => 20200203151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => METHOD OF HEATING SOC FILM ON WAFER AND HEATING APPARATUS USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/667802 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4298 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667802 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/667802
Method of heating SOC film on wafer by electromagnetic wave generator and heating apparatus using the same Oct 28, 2019 Issued
Array ( [id] => 15564449 [patent_doc_number] => 20200066636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => E-FUSE AND MANUFACTURING METHOD THEREOF, AND MEMORY CELL [patent_app_type] => utility [patent_app_number] => 16/664787 [patent_app_country] => US [patent_app_date] => 2019-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6793 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16664787 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/664787
E-fuse and manufacturing method thereof, and memory cell Oct 24, 2019 Issued
Array ( [id] => 15503331 [patent_doc_number] => 20200051854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => INTERCONNECT STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/657169 [patent_app_country] => US [patent_app_date] => 2019-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4298 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16657169 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/657169
Interconnect structure Oct 17, 2019 Issued
Array ( [id] => 16780655 [patent_doc_number] => 20210117734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => GATED TRUNCATED READOUT SYSTEM [patent_app_type] => utility [patent_app_number] => 16/656740 [patent_app_country] => US [patent_app_date] => 2019-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16656740 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/656740
Gated truncated readout system Oct 17, 2019 Issued
Array ( [id] => 15504027 [patent_doc_number] => 20200052202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => METHODS OF FORMING SILICON-CONTAINING DIELECTRIC MATERIALS AND METHODS OF FORMING A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/655672 [patent_app_country] => US [patent_app_date] => 2019-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5082 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16655672 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/655672
Methods of forming silicon-containing dielectric materials and methods of forming a semiconductor device comprising nitrogen radicals and oxygen-containing, silicon-containing, or carbon-containing precursors Oct 16, 2019 Issued
Array ( [id] => 17217692 [patent_doc_number] => 20210351030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => STRUCTURE MANUFACTURING METHOD AND STRUCTURE MANUFACTURING DEVICE [patent_app_type] => utility [patent_app_number] => 17/286198 [patent_app_country] => US [patent_app_date] => 2019-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32039 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17286198 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/286198
Structure manufacturing method including surface photoelectrochemical etching and structure manufacturing device Oct 16, 2019 Issued
Array ( [id] => 16574921 [patent_doc_number] => 10896848 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-19 [patent_title] => Method of manufacturing a semiconductor device [patent_app_type] => utility [patent_app_number] => 16/653975 [patent_app_country] => US [patent_app_date] => 2019-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 3849 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16653975 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/653975
Method of manufacturing a semiconductor device Oct 14, 2019 Issued
Array ( [id] => 16609326 [patent_doc_number] => 10910340 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-02 [patent_title] => Silver sintering preparation and the use thereof for the connecting of electronic components [patent_app_type] => utility [patent_app_number] => 16/601375 [patent_app_country] => US [patent_app_date] => 2019-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4952 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16601375 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/601375
Silver sintering preparation and the use thereof for the connecting of electronic components Oct 13, 2019 Issued
Array ( [id] => 17025695 [patent_doc_number] => 20210249567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => LID MATERIAL FOR PACKAGES, AND PACKAGE [patent_app_type] => utility [patent_app_number] => 17/260276 [patent_app_country] => US [patent_app_date] => 2019-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6739 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17260276 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/260276
Lid material for packages including reflowed gold-tin layers, and method for manufacturing package Oct 8, 2019 Issued
Array ( [id] => 15442789 [patent_doc_number] => 20200035578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => Die-on-Interposer Assembly with Dam Structure and Method of Manufacturing the Same [patent_app_type] => utility [patent_app_number] => 16/593495 [patent_app_country] => US [patent_app_date] => 2019-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3890 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16593495 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/593495
Die-on-interposer assembly with dam structure and method of manufacturing the same Oct 3, 2019 Issued
Array ( [id] => 15985041 [patent_doc_number] => 10672860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Multi-terminal inductor for integrated circuit [patent_app_type] => utility [patent_app_number] => 16/587305 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 35 [patent_no_of_words] => 10488 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16587305 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/587305
Multi-terminal inductor for integrated circuit Sep 29, 2019 Issued
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