Search

John P. Dulka

Examiner (ID: 18278, Phone: (571)270-7398 , Office: P/2895 )

Most Active Art Unit
2895
Art Unit(s)
2817, 2895
Total Applications
1000
Issued Applications
819
Pending Applications
77
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15331937 [patent_doc_number] => 20200006298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => LIGHT EMITTING DIODE PACKAGE AND LIGHT EMITTING DIODE MODULE [patent_app_type] => utility [patent_app_number] => 16/566823 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4878 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566823 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/566823
Light emitting diode package and light emitting diode module Sep 9, 2019 Issued
Array ( [id] => 17002822 [patent_doc_number] => 11081645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Mask assembly with surface roughened mask sheet at welding location, method of manufacturing the same, and method of manufacturing display device using the same [patent_app_type] => utility [patent_app_number] => 16/563619 [patent_app_country] => US [patent_app_date] => 2019-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 6999 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16563619 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/563619
Mask assembly with surface roughened mask sheet at welding location, method of manufacturing the same, and method of manufacturing display device using the same Sep 5, 2019 Issued
Array ( [id] => 15840745 [patent_doc_number] => 20200135655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => Graphene Layer for Reduced Contact Resistance [patent_app_type] => utility [patent_app_number] => 16/560585 [patent_app_country] => US [patent_app_date] => 2019-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16560585 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/560585
Graphene layer for reduced contact resistance Sep 3, 2019 Issued
Array ( [id] => 15597811 [patent_doc_number] => 20200075440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/560493 [patent_app_country] => US [patent_app_date] => 2019-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12803 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16560493 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/560493
Semiconductor device with recessed end surface of lead Sep 3, 2019 Issued
Array ( [id] => 16553130 [patent_doc_number] => 10886295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Semiconductor storage device [patent_app_type] => utility [patent_app_number] => 16/560606 [patent_app_country] => US [patent_app_date] => 2019-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 9099 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16560606 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/560606
Semiconductor storage device Sep 3, 2019 Issued
Array ( [id] => 16210505 [patent_doc_number] => 20200243495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => MULTI-LAYER POWER CONVERTER WITH DEVICES HAVING REDUCED LATERAL CURRENT [patent_app_type] => utility [patent_app_number] => 16/558679 [patent_app_country] => US [patent_app_date] => 2019-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6627 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16558679 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/558679
Multi-layer power converter with devices having reduced lateral current Sep 2, 2019 Issued
Array ( [id] => 17683369 [patent_doc_number] => 11367634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-21 [patent_title] => Substrate treating apparatus with edge treating unit and substrate treating method [patent_app_type] => utility [patent_app_number] => 16/557790 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 6528 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16557790 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/557790
Substrate treating apparatus with edge treating unit and substrate treating method Aug 29, 2019 Issued
Array ( [id] => 15597697 [patent_doc_number] => 20200075383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => CERAMICS SUBSTRATE AND ELECTROSTATIC CHUCK [patent_app_type] => utility [patent_app_number] => 16/555011 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6084 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16555011 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/555011
Ceramic substrate containing aluminum oxide and electrostatic chuck having electrode containing tungsten with oxides Aug 28, 2019 Issued
Array ( [id] => 17559189 [patent_doc_number] => 11315911 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Combined display panel with overlapping sub-screens [patent_app_type] => utility [patent_app_number] => 16/617513 [patent_app_country] => US [patent_app_date] => 2019-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2820 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16617513 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/617513
Combined display panel with overlapping sub-screens Aug 22, 2019 Issued
Array ( [id] => 15929109 [patent_doc_number] => 20200156188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => STAGE FOR CUTTING SUBSTRATE AND SUBSTRATE-CUTTING APPARATUS [patent_app_type] => utility [patent_app_number] => 16/547354 [patent_app_country] => US [patent_app_date] => 2019-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16547354 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/547354
Stage for cutting substrate including removable tube line and substrate-cutting apparatus therof Aug 20, 2019 Issued
Array ( [id] => 16660715 [patent_doc_number] => 20210057352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => FAN-OUT PACKAGE WITH REINFORCING RIVETS [patent_app_type] => utility [patent_app_number] => 16/544021 [patent_app_country] => US [patent_app_date] => 2019-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6736 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16544021 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/544021
Fan-out package with reinforcing rivets Aug 18, 2019 Issued
Array ( [id] => 16566976 [patent_doc_number] => 10892353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Semiconductor device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/543106 [patent_app_country] => US [patent_app_date] => 2019-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 11429 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16543106 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/543106
Semiconductor device and method of manufacturing the same Aug 15, 2019 Issued
Array ( [id] => 15841157 [patent_doc_number] => 20200135861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => Transistors with Stacked Semiconductor Layers as Channels [patent_app_type] => utility [patent_app_number] => 16/542523 [patent_app_country] => US [patent_app_date] => 2019-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7178 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16542523 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/542523
Transistors with stacked semiconductor layers as channels Aug 15, 2019 Issued
Array ( [id] => 16631654 [patent_doc_number] => 20210050307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME [patent_app_type] => utility [patent_app_number] => 16/542305 [patent_app_country] => US [patent_app_date] => 2019-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6685 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16542305 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/542305
Semiconductor device and method of fabricating same including two seal rings Aug 15, 2019 Issued
Array ( [id] => 16631758 [patent_doc_number] => 20210050411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => SEMICONDUCTOR SUBSTRATE INCLUDING STRESS MEMORIZATION LAYER [patent_app_type] => utility [patent_app_number] => 16/542667 [patent_app_country] => US [patent_app_date] => 2019-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16542667 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/542667
Method of forming stress memorization layer on backside of semiconductor substrate and semiconductor device thereof Aug 15, 2019 Issued
Array ( [id] => 16631790 [patent_doc_number] => 20210050443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => Integrated Assemblies Containing Two-Dimensional Materials [patent_app_type] => utility [patent_app_number] => 16/542078 [patent_app_country] => US [patent_app_date] => 2019-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16542078 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/542078
Transistors, memory structures and memory arrays containing two-dimensional materials between a source/drain region and a channel region Aug 14, 2019 Issued
Array ( [id] => 16594181 [patent_doc_number] => 10903459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Mask assembly, and apparatus and method for manufacturing display apparatus including the mask assembly [patent_app_type] => utility [patent_app_number] => 16/534363 [patent_app_country] => US [patent_app_date] => 2019-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8729 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16534363 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/534363
Mask assembly, and apparatus and method for manufacturing display apparatus including the mask assembly Aug 6, 2019 Issued
Array ( [id] => 16080561 [patent_doc_number] => 20200194267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/533370 [patent_app_country] => US [patent_app_date] => 2019-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18185 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16533370 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/533370
Semiconductor device and method for fabricating the same including re-growth process to form non-uniform gate dielectric layer Aug 5, 2019 Issued
Array ( [id] => 16819900 [patent_doc_number] => 11004738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Capacitance reduction by metal cut design [patent_app_type] => utility [patent_app_number] => 16/531232 [patent_app_country] => US [patent_app_date] => 2019-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 10867 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16531232 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/531232
Capacitance reduction by metal cut design Aug 4, 2019 Issued
Array ( [id] => 18235941 [patent_doc_number] => 11600505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Systems and methods for systematic physical failure analysis (PFA) fault localization [patent_app_type] => utility [patent_app_number] => 16/527435 [patent_app_country] => US [patent_app_date] => 2019-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16527435 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/527435
Systems and methods for systematic physical failure analysis (PFA) fault localization Jul 30, 2019 Issued
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