Search

John P. Dulka

Examiner (ID: 18278, Phone: (571)270-7398 , Office: P/2895 )

Most Active Art Unit
2895
Art Unit(s)
2817, 2895
Total Applications
1000
Issued Applications
819
Pending Applications
77
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15108627 [patent_doc_number] => 10475644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Dielectric-metal stack for 3D flash memory application [patent_app_type] => utility [patent_app_number] => 15/959646 [patent_app_country] => US [patent_app_date] => 2018-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4764 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15959646 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/959646
Dielectric-metal stack for 3D flash memory application Apr 22, 2018 Issued
Array ( [id] => 16609271 [patent_doc_number] => 10910285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Package structure with TFTS and die covered RDL [patent_app_type] => utility [patent_app_number] => 15/943736 [patent_app_country] => US [patent_app_date] => 2018-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8667 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15943736 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/943736
Package structure with TFTS and die covered RDL Apr 2, 2018 Issued
Array ( [id] => 14205391 [patent_doc_number] => 10269820 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-23 [patent_title] => Three-dimensional memory device containing different pedestal width support pillar structures and method of making the same [patent_app_type] => utility [patent_app_number] => 15/943859 [patent_app_country] => US [patent_app_date] => 2018-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 41 [patent_no_of_words] => 19573 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15943859 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/943859
Three-dimensional memory device containing different pedestal width support pillar structures and method of making the same Apr 2, 2018 Issued
Array ( [id] => 14446347 [patent_doc_number] => 20190181047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => STRUCTURE AND METHOD OF FORMING SELF ALIGNED CONTACTS IN SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/944027 [patent_app_country] => US [patent_app_date] => 2018-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4320 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15944027 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/944027
Structure and method of forming self aligned contacts in semiconductor device Apr 2, 2018 Issued
Array ( [id] => 14526203 [patent_doc_number] => 10340372 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-02 [patent_title] => Transistor device having a pillar structure [patent_app_type] => utility [patent_app_number] => 15/943914 [patent_app_country] => US [patent_app_date] => 2018-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 7959 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15943914 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/943914
Transistor device having a pillar structure Apr 2, 2018 Issued
Array ( [id] => 13334979 [patent_doc_number] => 20180219027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => THIN-FILM-TRANSISTOR (TFT) ARRAY PANEL WITH STRESS ELIMINATION LAYER AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/937866 [patent_app_country] => US [patent_app_date] => 2018-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3062 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15937866 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/937866
Thin-film-transistor (TFT) array panel with stress elimination layer and method of manufacturing the same Mar 27, 2018 Issued
Array ( [id] => 15766941 [patent_doc_number] => 20200114488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => METHOD FOR POLISHING SILICON WAFER [patent_app_type] => utility [patent_app_number] => 16/603886 [patent_app_country] => US [patent_app_date] => 2018-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2928 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16603886 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/603886
Method for polishing silicon wafer Mar 15, 2018 Issued
Array ( [id] => 13132229 [patent_doc_number] => 10084054 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-25 [patent_title] => Field effect transistor which can be biased to achieve a uniform depletion region [patent_app_type] => utility [patent_app_number] => 15/920250 [patent_app_country] => US [patent_app_date] => 2018-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6365 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15920250 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/920250
Field effect transistor which can be biased to achieve a uniform depletion region Mar 12, 2018 Issued
Array ( [id] => 13303551 [patent_doc_number] => 20180203312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/915663 [patent_app_country] => US [patent_app_date] => 2018-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22435 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15915663 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/915663
Display device Mar 7, 2018 Issued
Array ( [id] => 14036541 [patent_doc_number] => 10230029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Light emitting device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/932184 [patent_app_country] => US [patent_app_date] => 2018-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 29 [patent_no_of_words] => 19861 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15932184 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/932184
Light emitting device and method of manufacturing the same Feb 15, 2018 Issued
Array ( [id] => 15462551 [patent_doc_number] => 20200044100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => Method For Texturing A Surface Of A Semiconductor Material And Device For Carrying Out The Method [patent_app_type] => utility [patent_app_number] => 16/484849 [patent_app_country] => US [patent_app_date] => 2018-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16484849 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/484849
Method For Texturing A Surface Of A Semiconductor Material And Device For Carrying Out The Method Feb 7, 2018 Abandoned
Array ( [id] => 13435041 [patent_doc_number] => 20180269063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/883393 [patent_app_country] => US [patent_app_date] => 2018-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8648 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15883393 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/883393
Method of manufacturing semiconductor device using photoresist as ion implantation mask Jan 29, 2018 Issued
Array ( [id] => 13349771 [patent_doc_number] => 20180226425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => ACCOMMODATING IMPERFECTLY ALIGNED MEMORY HOLES [patent_app_type] => utility [patent_app_number] => 15/882454 [patent_app_country] => US [patent_app_date] => 2018-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15882454 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/882454
Accommodating imperfectly aligned memory holes Jan 28, 2018 Issued
Array ( [id] => 16241891 [patent_doc_number] => 20200259125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => METHOD FOR FORMING AN ORGANIC ELECTROLUMINESCENCE (EL) ELEMENT [patent_app_type] => utility [patent_app_number] => 16/481603 [patent_app_country] => US [patent_app_date] => 2018-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16481603 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/481603
Method for forming an organic electroluminescence (EL) element with annealing temperatures for different pixels Jan 28, 2018 Issued
Array ( [id] => 14397749 [patent_doc_number] => 10312165 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-04 [patent_title] => Micro lighting device [patent_app_type] => utility [patent_app_number] => 15/881799 [patent_app_country] => US [patent_app_date] => 2018-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2880 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15881799 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/881799
Micro lighting device Jan 27, 2018 Issued
Array ( [id] => 14676431 [patent_doc_number] => 20190237330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => SPACER PROFILE CONTROL USING ATOMIC LAYER DEPOSITION IN A MULTIPLE PATTERNING PROCESS [patent_app_type] => utility [patent_app_number] => 15/881506 [patent_app_country] => US [patent_app_date] => 2018-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15989 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15881506 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/881506
Spacer profile control using atomic layer deposition in a multiple patterning process Jan 25, 2018 Issued
Array ( [id] => 15240501 [patent_doc_number] => 20190375036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => SOLDERING SYSTEM, CONTROL DEVICE, CONTROL METHOD, AND PROGRAM [patent_app_type] => utility [patent_app_number] => 16/476431 [patent_app_country] => US [patent_app_date] => 2018-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9164 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16476431 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/476431
Soldering system including temperature distribution measurement control device, control method, and program Jan 25, 2018 Issued
Array ( [id] => 15139769 [patent_doc_number] => 10483372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Spacer structure with high plasma resistance for semiconductor devices [patent_app_type] => utility [patent_app_number] => 15/874278 [patent_app_country] => US [patent_app_date] => 2018-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 30 [patent_no_of_words] => 8131 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15874278 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/874278
Spacer structure with high plasma resistance for semiconductor devices Jan 17, 2018 Issued
Array ( [id] => 18101592 [patent_doc_number] => 11541464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Method for manufacturing diamond single crystal cutting tool using laser pulses [patent_app_type] => utility [patent_app_number] => 16/499049 [patent_app_country] => US [patent_app_date] => 2018-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4940 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16499049 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/499049
Method for manufacturing diamond single crystal cutting tool using laser pulses Jan 9, 2018 Issued
Array ( [id] => 13043037 [patent_doc_number] => 10043658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-07 [patent_title] => Precursors for silicon dioxide gap fill [patent_app_type] => utility [patent_app_number] => 15/862205 [patent_app_country] => US [patent_app_date] => 2018-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 7534 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15862205 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/862205
Precursors for silicon dioxide gap fill Jan 3, 2018 Issued
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