Search

John P. Dulka

Examiner (ID: 18278, Phone: (571)270-7398 , Office: P/2895 )

Most Active Art Unit
2895
Art Unit(s)
2817, 2895
Total Applications
1000
Issued Applications
819
Pending Applications
77
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12693121 [patent_doc_number] => 20180122873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => LIGHT EMITTING DEVICE INCLUDING TANDEM STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/862157 [patent_app_country] => US [patent_app_date] => 2018-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9566 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15862157 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/862157
Light emitting device including tandem structure with quantum dots and nanoparticles Jan 3, 2018 Issued
Array ( [id] => 16746392 [patent_doc_number] => 10971393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Metal-insulator-metal (MIM) structure supporting high voltage applications and low voltage applications [patent_app_type] => utility [patent_app_number] => 16/649081 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 11368 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16649081 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/649081
Metal-insulator-metal (MIM) structure supporting high voltage applications and low voltage applications Dec 26, 2017 Issued
Array ( [id] => 12631365 [patent_doc_number] => 20180102285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => METHODS OF FABRICATING A SEMICONDUCTOR DEVICE HAVING A VIA STRUCTURE AND AN INTERCONNECTION STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/837132 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15837132 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/837132
Methods of fabricating a semiconductor device having a via structure and an interconnection structure Dec 10, 2017 Issued
Array ( [id] => 16738940 [patent_doc_number] => 10964604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Magnetic storage element, magnetic storage device, electronic device, and method of manufacturing magnetic storage element [patent_app_type] => utility [patent_app_number] => 16/486555 [patent_app_country] => US [patent_app_date] => 2017-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 12821 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16486555 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/486555
Magnetic storage element, magnetic storage device, electronic device, and method of manufacturing magnetic storage element Dec 7, 2017 Issued
Array ( [id] => 12595623 [patent_doc_number] => 20180090371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => INTERCONNECT STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/825646 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4298 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15825646 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/825646
Copper interconnect structure with manganese oxide barrier layer Nov 28, 2017 Issued
Array ( [id] => 12263698 [patent_doc_number] => 20180082894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'INTERCONNECT STRUCTURE' [patent_app_type] => utility [patent_app_number] => 15/825889 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4384 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15825889 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/825889
Copper interconnect structure with manganese oxide barrier layer Nov 28, 2017 Issued
Array ( [id] => 14558701 [patent_doc_number] => 10347824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Composite free layer for magnetoresistive random access memory [patent_app_type] => utility [patent_app_number] => 15/820274 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 10839 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15820274 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/820274
Composite free layer for magnetoresistive random access memory Nov 20, 2017 Issued
Array ( [id] => 13145899 [patent_doc_number] => 10090289 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-02 [patent_title] => Integrated circuits with standard cell [patent_app_type] => utility [patent_app_number] => 15/813163 [patent_app_country] => US [patent_app_date] => 2017-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3411 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15813163 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/813163
Integrated circuits with standard cell Nov 14, 2017 Issued
Array ( [id] => 15061701 [patent_doc_number] => 10461163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Three-dimensional memory device with thickened word lines in terrace region and method of making thereof [patent_app_type] => utility [patent_app_number] => 15/813579 [patent_app_country] => US [patent_app_date] => 2017-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 65 [patent_no_of_words] => 28447 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15813579 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/813579
Three-dimensional memory device with thickened word lines in terrace region and method of making thereof Nov 14, 2017 Issued
Array ( [id] => 14387637 [patent_doc_number] => 10307072 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-04 [patent_title] => Reducing noise levels associated with sensed ECG signals [patent_app_type] => utility [patent_app_number] => 15/813359 [patent_app_country] => US [patent_app_date] => 2017-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3800 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15813359 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/813359
Reducing noise levels associated with sensed ECG signals Nov 14, 2017 Issued
Array ( [id] => 13159741 [patent_doc_number] => 10096606 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-09 [patent_title] => Methods of forming a gate structure-to-source/drain conductive contact on vertical transistor devices and the resulting transistor devices [patent_app_type] => utility [patent_app_number] => 15/813471 [patent_app_country] => US [patent_app_date] => 2017-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4994 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15813471 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/813471
Methods of forming a gate structure-to-source/drain conductive contact on vertical transistor devices and the resulting transistor devices Nov 14, 2017 Issued
Array ( [id] => 14317251 [patent_doc_number] => 20190148329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => Interconnect Chips [patent_app_type] => utility [patent_app_number] => 15/813538 [patent_app_country] => US [patent_app_date] => 2017-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6839 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15813538 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/813538
Interconnect chips Nov 14, 2017 Issued
Array ( [id] => 16637910 [patent_doc_number] => 10916425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Method for manufacturing silicon single crystal, flow straightening member, and single crystal pulling device [patent_app_type] => utility [patent_app_number] => 16/484619 [patent_app_country] => US [patent_app_date] => 2017-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5021 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16484619 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/484619
Method for manufacturing silicon single crystal, flow straightening member, and single crystal pulling device Nov 13, 2017 Issued
Array ( [id] => 12243160 [patent_doc_number] => 20180076023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'High Temperature Silicon Oxide Atomic Layer Deposition Technology' [patent_app_type] => utility [patent_app_number] => 15/805831 [patent_app_country] => US [patent_app_date] => 2017-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10730 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15805831 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/805831
High temperature silicon oxide atomic layer deposition technology Nov 6, 2017 Issued
Array ( [id] => 12243373 [patent_doc_number] => 20180076236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'Flexible Display Device with Wire Having Reinforced Portion and Manufacturing Method for the Same' [patent_app_type] => utility [patent_app_number] => 15/803638 [patent_app_country] => US [patent_app_date] => 2017-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14576 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15803638 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/803638
Flexible display device with wire having reinforced portion and manufacturing method for the same Nov 2, 2017 Issued
Array ( [id] => 13154641 [patent_doc_number] => 10094035 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-09 [patent_title] => Convection optimization for mixed feature electroplating [patent_app_type] => utility [patent_app_number] => 15/785251 [patent_app_country] => US [patent_app_date] => 2017-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 27 [patent_no_of_words] => 16656 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15785251 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/785251
Convection optimization for mixed feature electroplating Oct 15, 2017 Issued
Array ( [id] => 12159045 [patent_doc_number] => 20180030312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'DIRECTED SELF-ASSEMBLY' [patent_app_type] => utility [patent_app_number] => 15/728877 [patent_app_country] => US [patent_app_date] => 2017-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3325 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15728877 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/728877
Directed self-assembly Oct 9, 2017 Issued
Array ( [id] => 18120523 [patent_doc_number] => 11551922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Method of polishing silicon wafer including notch polishing process and method of producing silicon wafer [patent_app_type] => utility [patent_app_number] => 16/467273 [patent_app_country] => US [patent_app_date] => 2017-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6128 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16467273 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/467273
Method of polishing silicon wafer including notch polishing process and method of producing silicon wafer Sep 21, 2017 Issued
Array ( [id] => 14367103 [patent_doc_number] => 10304865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Pixel array substrate with discontinuous selection lines [patent_app_type] => utility [patent_app_number] => 15/712170 [patent_app_country] => US [patent_app_date] => 2017-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3344 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15712170 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/712170
Pixel array substrate with discontinuous selection lines Sep 21, 2017 Issued
Array ( [id] => 12589782 [patent_doc_number] => 20180088423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => LIQUID CRYSTAL DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/708417 [patent_app_country] => US [patent_app_date] => 2017-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6193 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15708417 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/708417
Liquid crystal display device including alternating colors in column Sep 18, 2017 Issued
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